Burst Architecture Specification Sheet
Table Of Contents
- Features
- Configurations
- Functional Description
- Selection Guide
- Logic Block Diagram (CY7C1392CV18)
- Logic Block Diagram (CY7C1992CV18)
- Logic Block Diagram (CY7C1393CV18)
- Logic Block Diagram (CY7C1394CV18)
- Pin Configuration
- Pin Definitions
- Functional Overview
- Application Example
- Truth Table
- Write Cycle Descriptions
- Write Cycle Descriptions
- Write Cycle Descriptions
- IEEE 1149.1 Serial Boundary Scan (JTAG)
- TAP Controller State Diagram
- TAP Controller Block Diagram
- TAP Electrical Characteristics
- TAP AC Switching Characteristics
- TAP Timing and Test Conditions
- Identification Register Definitions
- Scan Register Sizes
- Instruction Codes
- Boundary Scan Order
- Power Up Sequence in DDR-II SRAM
- Maximum Ratings
- Operating Range
- Electrical Characteristics
- Capacitance
- Thermal Resistance
- Switching Characteristics
- Switching Waveforms
- Ordering Information
- Package Diagram
- Document History Page
- Sales, Solutions, and Legal Information
CY7C1392CV18, CY7C1992CV18
CY7C1393CV18, CY7C1394CV18
Document #: 001-07162 Rev. *C Page 3 of 30
Logic Block Diagram (CY7C1393CV18)
Logic Block Diagram (CY7C1394CV18)
512K x 18 Array
CLK
A
(18:0)
Gen.
K
K
Control
Logic
Address
Register
D
[17:0]
Read Add. Decode
Read Data Reg.
LD
Q
[17:0]
Reg.
Reg.
Reg.
18
36
18
BWS
[1:0]
V
REF
Write Add. Decode
Write
Data Reg
18
18
19
18
R/W
LD
R/W
CQ
CQ
DOFF
512K x 18 Array
Write
Data Reg
Control
Logic
C
C
18
256K x 18 Array
CLK
A
(17:0)
Gen.
K
K
Control
Logic
Address
Register
D
[35:0]
Read Add. Decode
Read Data Reg.
LD
Q
[35:0]
Reg.
Reg.
Reg.
36
72
36
BWS
[3:0]
V
REF
Write Add. Decode
Write
Data Reg
36
36
18
36
R/W
LD
R/W
CQ
CQ
DOFF
256K x 18 Array
Write
Data Reg
Control
Logic
C
C
36
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