Burst Architecture Specification Sheet
Table Of Contents
- Features
- Configurations
- Functional Description
- Selection Guide
- Logic Block Diagram (CY7C1392CV18)
- Logic Block Diagram (CY7C1992CV18)
- Logic Block Diagram (CY7C1393CV18)
- Logic Block Diagram (CY7C1394CV18)
- Pin Configuration
- Pin Definitions
- Functional Overview
- Application Example
- Truth Table
- Write Cycle Descriptions
- Write Cycle Descriptions
- Write Cycle Descriptions
- IEEE 1149.1 Serial Boundary Scan (JTAG)
- TAP Controller State Diagram
- TAP Controller Block Diagram
- TAP Electrical Characteristics
- TAP AC Switching Characteristics
- TAP Timing and Test Conditions
- Identification Register Definitions
- Scan Register Sizes
- Instruction Codes
- Boundary Scan Order
- Power Up Sequence in DDR-II SRAM
- Maximum Ratings
- Operating Range
- Electrical Characteristics
- Capacitance
- Thermal Resistance
- Switching Characteristics
- Switching Waveforms
- Ordering Information
- Package Diagram
- Document History Page
- Sales, Solutions, and Legal Information
CY7C1392CV18, CY7C1992CV18
CY7C1393CV18, CY7C1394CV18
Document #: 001-07162 Rev. *C Page 25 of 30
Switching Waveforms
Figure 5. Read/Write/Deselect Sequence
[27, 28, 29]
K
1234567
8
K
LD
R/W
A
Q
D
C
C#
READ
(burst of 2)
READ
(burst of 2)
READ
(burst of 2)
WRITE
(burst of 2)
WRITE
(burst of 2)
t
KHCH
t
KHCH
NOP
NOP
CQ
CQ#
t
KH
t
KHKH
t
CO
t
KL
t
CYC
t
t
HC
t
SA
t
HA
t
SD
t
HD
t
SD
t
HD
t
CLZ
t
DOH
SC
t
KH
t
KHKH
t
KL
t
CYC
t
CQD
t
CCQO
t
CQOH
t
CCQO
t
CQOH
DON’T CARE UNDEFINED
A0 A1 A2
A3 A4
D20 D21 D30 D31
Q40
Q11Q10
Q41
Q00
Q01
t
CQDOH
t
CQH
t
CQHCQH
t
CHZ
Notes
27. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1.
28. Outputs are disabled (High-Z) one clock cycle after a NOP.
29. In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram.
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