Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade Support Specification Sheet
Table Of Contents
- EZ-Host Features
- Typical Applications
- Introduction
- Functional Overview
- Interface Descriptions
- USB Interface
- OTG Interface
- External Memory Interface
- General Purpose IO Interface (GPIO)
- UART Interface
- I2C EEPROM Interface
- Serial Peripheral Interface
- High-Speed Serial Interface
- Programmable Pulse/PWM Interface
- Host Port Interface
- IDE Interface
- Charge Pump Interface
- Booster Interface
- Crystal Interface
- Boot Configuration Interface
- Operational Modes
- Power Savings and Reset Description
- Memory Map
- Registers
- Processor Control Registers
- CPU Flags Register [0xC000] [R]
- Bank Register [0xC002] [R/W]
- Hardware Revision Register [0xC004] [R]
- CPU Speed Register [0xC008] [R/W]
- Power Control Register [0xC00A] [R/W]
- Interrupt Enable Register [0xC00E] [R/W]
- Breakpoint Register [0xC014] [R/W]
- USB Diagnostic Register [0xC03C] [R/W]
- Memory Diagnostic Register [0xC03E] [W]
- External Memory Registers
- Timer Registers
- General USB Registers
- USB Host Only Registers
- Host n Control Register [R/W]
- Host n Address Register [R/W]
- Host n Count Register [R/W]
- Host n Endpoint Status Register [R]
- Host n PID Register [W]
- Host n Count Result Register [R]
- Host n Device Address Register [W]
- Host n Interrupt Enable Register [R/W]
- Host n Status Register [R/W]
- Host n SOF/EOP Count Register [R/W]
- Host n SOF/EOP Counter Register [R]
- Host n Frame Register [R]
- USB Device Only Registers
- Device n Endpoint n Control Register [R/W]
- Device n Endpoint n Address Register [R/W]
- Device n Endpoint n Count Register [R/W]
- Device n Endpoint n Status Register [R/W]
- Device n Endpoint n Count Result Register [R/W]
- Device n Port Select Register [R/W]
- Device n Interrupt Enable Register [R/W]
- Device n Address Register [W]
- Device n Status Register [R/W]
- Device n Frame Number Register [R]
- Device n SOF/EOP Count Register [W]
- OTG Control Registers
- GPIO Registers
- IDE Registers
- HSS Registers
- HSS Control Register [0xC070] [R/W]
- HSS Baud Rate Register [0xC072] [R/W]
- HSS Transmit Gap Register [0xC074] [R/W]
- HSS Data Register [0xC076] [R/W]
- HSS Receive Address Register [0xC078] [R/W]
- HSS Receive Counter Register [0xC07A] [R/W]
- HSS Transmit Address Register [0xC07C] [R/W]
- HSS Transmit Counter Register [0xC07E] [R/W]
- HPI Registers
- SPI Registers
- SPI Configuration Register [0xC0C8] [R/W]
- SPI Control Register [0xC0CA] [R/W]
- SPI Interrupt Enable Register [0xC0CC] [R/W]
- SPI Status Register [0xC0CE] [R]
- SPI Interrupt Clear Register [0xC0D0] [W]
- SPI CRC Control Register [0xC0D2] [R/W]
- SPI CRC Value Register [0xC0D4] [R/W]
- SPI Data Register [0xC0D6] [R/W]
- SPI Transmit Address Register [0xC0D8] [R/W]
- SPI Transmit Count Register [0xC0DA] [R/W]
- SPI Receive Address Register [0xC0DC [R/W]
- SPI Receive Count Register [0xC0DE] [R/W]
- UART Registers
- PWM Registers
- Processor Control Registers
- Pin Diagram
- Pin Descriptions
- Absolute Maximum Ratings
- Operating Conditions
- Crystal Requirements (XTALIN, XTALOUT)
- DC Characteristics
- AC Timing Characteristics
- Register Summary
- Ordering Information
- Package Diagrams
- Document History Page
- Sales, Solutions, and Legal Information
CY7C67300
Document #: 38-08015 Rev. *J Page 91 of 99
IDE Timing
The IDE interface supports PIO mode 0-4 as specified in the Information Technology-AT Attachment–4 with Packet Interface Extension
(ATA/ATAPI-4) Specification, T13/1153D Rev 18.
HSS BYTE Mode Transmit
qt_clk, CPU_A, CPUHSS_cs, CPU_wr are internal signals, included in the diagram to illustrate the relationship between CPU opera-
tions and HSS port operations.
Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_TxD HIGH = data bit value ‘1’.
BT = bit time = 1/baud rate.
HSS Block Mode Transmit
BLOCK mode transmit timing is similar to BYTE mode, except the STOP bit time is controlled by the HSS_GAP value.
The BLOCK mode STOP bit time, t
GAP
= (HSS_GAP – 9) BT, where BT is the bit time, and HSS_GAP is the content of the HSS
Transmit Gap register [0xC074].
The default t
GAP
is 2 BT.
BT = bit time = 1/baud rate.
HSS BYTE and BLOCK Mode Receive
Receive data arrives asynchronously relative to the internal clock. Incoming data bit rate may deviate from the programmed baud rate
clock by as much as ±5% (with HSS_RATE value of 23 or higher).
BYTE mode received bytes are buffered in a FIFO. The FIFO not empty condition becomes the RxRdy flag.
BLOCK mode received bytes are written directly to the memory system.
Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_RxD HIGH = data bit value ‘1’.
BT = bit time = 1/baud rate.
CPU may start another BYTE
transmit right after TxRdy
goes high
start of last data bit to TxRdy high:
0 min, 4 T max.
(T is qt_clk period)
TxRdy low to start bit delay:
0 min, BT max when starting from IDEL.
For back to back transmit, new START Bit
begins immediately following previous STOP bit.
(BT = bit period)
BT
BT
start bit bit 0
bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
qt_clk
CPU_A[2:0]
CPUHSS_cs
CPU_wr
TxRdy flag
HSS_TxD
Byte transmit
triggered by a
CPU write to the
HSS_TxData register
stop bit start bit
programmable
1 or 2 stop bits.
1 stop bit shown.
HSS_TxD
t
GAP
BT
BT +/- 5%
start bit bit 0
bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 stop bit start bit
HSS_RxD
BT +/- 5%
10 BT +/- 5%
received byte added to
receive FIFO during the final data bit time
[+] Feedback