Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade Support Specification Sheet
Table Of Contents
- EZ-Host Features
- Typical Applications
- Introduction
- Functional Overview
- Interface Descriptions
- USB Interface
- OTG Interface
- External Memory Interface
- General Purpose IO Interface (GPIO)
- UART Interface
- I2C EEPROM Interface
- Serial Peripheral Interface
- High-Speed Serial Interface
- Programmable Pulse/PWM Interface
- Host Port Interface
- IDE Interface
- Charge Pump Interface
- Booster Interface
- Crystal Interface
- Boot Configuration Interface
- Operational Modes
- Power Savings and Reset Description
- Memory Map
- Registers
- Processor Control Registers
- CPU Flags Register [0xC000] [R]
- Bank Register [0xC002] [R/W]
- Hardware Revision Register [0xC004] [R]
- CPU Speed Register [0xC008] [R/W]
- Power Control Register [0xC00A] [R/W]
- Interrupt Enable Register [0xC00E] [R/W]
- Breakpoint Register [0xC014] [R/W]
- USB Diagnostic Register [0xC03C] [R/W]
- Memory Diagnostic Register [0xC03E] [W]
- External Memory Registers
- Timer Registers
- General USB Registers
- USB Host Only Registers
- Host n Control Register [R/W]
- Host n Address Register [R/W]
- Host n Count Register [R/W]
- Host n Endpoint Status Register [R]
- Host n PID Register [W]
- Host n Count Result Register [R]
- Host n Device Address Register [W]
- Host n Interrupt Enable Register [R/W]
- Host n Status Register [R/W]
- Host n SOF/EOP Count Register [R/W]
- Host n SOF/EOP Counter Register [R]
- Host n Frame Register [R]
- USB Device Only Registers
- Device n Endpoint n Control Register [R/W]
- Device n Endpoint n Address Register [R/W]
- Device n Endpoint n Count Register [R/W]
- Device n Endpoint n Status Register [R/W]
- Device n Endpoint n Count Result Register [R/W]
- Device n Port Select Register [R/W]
- Device n Interrupt Enable Register [R/W]
- Device n Address Register [W]
- Device n Status Register [R/W]
- Device n Frame Number Register [R]
- Device n SOF/EOP Count Register [W]
- OTG Control Registers
- GPIO Registers
- IDE Registers
- HSS Registers
- HSS Control Register [0xC070] [R/W]
- HSS Baud Rate Register [0xC072] [R/W]
- HSS Transmit Gap Register [0xC074] [R/W]
- HSS Data Register [0xC076] [R/W]
- HSS Receive Address Register [0xC078] [R/W]
- HSS Receive Counter Register [0xC07A] [R/W]
- HSS Transmit Address Register [0xC07C] [R/W]
- HSS Transmit Counter Register [0xC07E] [R/W]
- HPI Registers
- SPI Registers
- SPI Configuration Register [0xC0C8] [R/W]
- SPI Control Register [0xC0CA] [R/W]
- SPI Interrupt Enable Register [0xC0CC] [R/W]
- SPI Status Register [0xC0CE] [R]
- SPI Interrupt Clear Register [0xC0D0] [W]
- SPI CRC Control Register [0xC0D2] [R/W]
- SPI CRC Value Register [0xC0D4] [R/W]
- SPI Data Register [0xC0D6] [R/W]
- SPI Transmit Address Register [0xC0D8] [R/W]
- SPI Transmit Count Register [0xC0DA] [R/W]
- SPI Receive Address Register [0xC0DC [R/W]
- SPI Receive Count Register [0xC0DE] [R/W]
- UART Registers
- PWM Registers
- Processor Control Registers
- Pin Diagram
- Pin Descriptions
- Absolute Maximum Ratings
- Operating Conditions
- Crystal Requirements (XTALIN, XTALOUT)
- DC Characteristics
- AC Timing Characteristics
- Register Summary
- Ordering Information
- Package Diagrams
- Document History Page
- Sales, Solutions, and Legal Information
CY7C67300
Document #: 38-08015 Rev. *J Page 80 of 99
71 D11/MOSI IO
D11: External Memory Data Bus
MOSI: SPI MOSI
72 D10/SCK IO
D10: External Memory Data Bus
SCK: SPI SCK
73 D9/nSSI IO
D9: External Memory Data Bus
nSSI: SPI nSSI
74 D8/MISO IO
D8: External Memory Data Bus
MISO: SPI MISO
76 D7 IO External Memory Data Bus
77 D6 IO
78 D5 IO
79 D4 IO
80 D3 IO
81 D2 IO
82 D1 IO
83 D0 IO
33 A14 Output External Memory Address Bus
32 A13 Output
31 A12 Output
30 A11 Output
27 A10 Output
25 A9 Output
24 A8 Output
20 A7 Output
17 A6 Output
8 A5 Output
7 A4 Output
3 A3 Output
2 A2 Output
1 A1 Output
99 nBEL/A0 Output
nBEL: Low Byte Enable for 16-bit memories
A0: External Memory Address bit A0 for 0-8 bit memories
98 nBEH Output High Byte Enable for 16-bit memories
64 nWR Output External Memory Write pulse
62 nRD Output External Memory Read pulse
97 A16 Output
A16: External SRAM A16
96 A17 Output
A17: External SRAM A17
95 A18 Output
A18: External SRAM A18
34 nXMEMSEL Output External Memory Select 0
35 nXROMSEL Output External Memory Select 1
36 nXRAMSEL Output External Memory Select 2
38 A15/CLKSEL IO
A15: External SRAM A15
CLKSEL: Sampled directly after reset to determine what crystal or
clock source frequency is being used. 12 MHz is required for normal
operation so the CLKSEL pin
must have a 47K ohm pull up to V
CC.
After reset this pin functions as A15.
39 GPIO31/SCK IO
GPIO31: General Purpose IO
SCK: I2C EEPROM SCK
40 GPIO30/SDA IO
GPIO30: General Purpose IO
SDA: I2C EEPROM SDA
Table 131. Pin Descriptions (continued)
Pin Name Type Description
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