Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade Support Specification Sheet
Table Of Contents
- EZ-Host Features
- Typical Applications
- Introduction
- Functional Overview
- Interface Descriptions
- USB Interface
- OTG Interface
- External Memory Interface
- General Purpose IO Interface (GPIO)
- UART Interface
- I2C EEPROM Interface
- Serial Peripheral Interface
- High-Speed Serial Interface
- Programmable Pulse/PWM Interface
- Host Port Interface
- IDE Interface
- Charge Pump Interface
- Booster Interface
- Crystal Interface
- Boot Configuration Interface
- Operational Modes
- Power Savings and Reset Description
- Memory Map
- Registers
- Processor Control Registers
- CPU Flags Register [0xC000] [R]
- Bank Register [0xC002] [R/W]
- Hardware Revision Register [0xC004] [R]
- CPU Speed Register [0xC008] [R/W]
- Power Control Register [0xC00A] [R/W]
- Interrupt Enable Register [0xC00E] [R/W]
- Breakpoint Register [0xC014] [R/W]
- USB Diagnostic Register [0xC03C] [R/W]
- Memory Diagnostic Register [0xC03E] [W]
- External Memory Registers
- Timer Registers
- General USB Registers
- USB Host Only Registers
- Host n Control Register [R/W]
- Host n Address Register [R/W]
- Host n Count Register [R/W]
- Host n Endpoint Status Register [R]
- Host n PID Register [W]
- Host n Count Result Register [R]
- Host n Device Address Register [W]
- Host n Interrupt Enable Register [R/W]
- Host n Status Register [R/W]
- Host n SOF/EOP Count Register [R/W]
- Host n SOF/EOP Counter Register [R]
- Host n Frame Register [R]
- USB Device Only Registers
- Device n Endpoint n Control Register [R/W]
- Device n Endpoint n Address Register [R/W]
- Device n Endpoint n Count Register [R/W]
- Device n Endpoint n Status Register [R/W]
- Device n Endpoint n Count Result Register [R/W]
- Device n Port Select Register [R/W]
- Device n Interrupt Enable Register [R/W]
- Device n Address Register [W]
- Device n Status Register [R/W]
- Device n Frame Number Register [R]
- Device n SOF/EOP Count Register [W]
- OTG Control Registers
- GPIO Registers
- IDE Registers
- HSS Registers
- HSS Control Register [0xC070] [R/W]
- HSS Baud Rate Register [0xC072] [R/W]
- HSS Transmit Gap Register [0xC074] [R/W]
- HSS Data Register [0xC076] [R/W]
- HSS Receive Address Register [0xC078] [R/W]
- HSS Receive Counter Register [0xC07A] [R/W]
- HSS Transmit Address Register [0xC07C] [R/W]
- HSS Transmit Counter Register [0xC07E] [R/W]
- HPI Registers
- SPI Registers
- SPI Configuration Register [0xC0C8] [R/W]
- SPI Control Register [0xC0CA] [R/W]
- SPI Interrupt Enable Register [0xC0CC] [R/W]
- SPI Status Register [0xC0CE] [R]
- SPI Interrupt Clear Register [0xC0D0] [W]
- SPI CRC Control Register [0xC0D2] [R/W]
- SPI CRC Value Register [0xC0D4] [R/W]
- SPI Data Register [0xC0D6] [R/W]
- SPI Transmit Address Register [0xC0D8] [R/W]
- SPI Transmit Count Register [0xC0DA] [R/W]
- SPI Receive Address Register [0xC0DC [R/W]
- SPI Receive Count Register [0xC0DE] [R/W]
- UART Registers
- PWM Registers
- Processor Control Registers
- Pin Diagram
- Pin Descriptions
- Absolute Maximum Ratings
- Operating Conditions
- Crystal Requirements (XTALIN, XTALOUT)
- DC Characteristics
- AC Timing Characteristics
- Register Summary
- Ordering Information
- Package Diagrams
- Document History Page
- Sales, Solutions, and Legal Information
CY7C67300
Document #: 38-08015 Rev. *J Page 75 of 99
PWM Registers
There are eleven registers dedicated to PWM operation. Each of these registers are covered in this section and summarized in
Table 124.
PWM Control Register [0xC0E6] [R/W]
Register Description
The PWM Control register provides high level control over all four
of the PWM channels.
PWM Enable (Bit 15)
The PWM Enable bit starts and stops PWM operation.
1: Start operation
0: Stop operation
Prescale Select (Bits [11:9])
The Prescale Select field sets the frequency of all the PWM
channels as defined in Table 126.
Table 124. PWM Registers
Register Name Address R/W
PWM Control Register 0xC0E6 R/W
PWM Maximum Count Register 0xC0E8 R/W
PWM0 Start Register 0xC0EA R/W
PWM0 Stop Register 0xC0EC R/W
PWM1 Start Register 0xC0EE R/W
PWM1 Stop Register 0xC0F0 R/W
PWM2 Start Register 0xC0F2 R/W
PWM2 Stop Register 0xC0F4 R/W
PWM3 Start Register 0xC0F6 R/W
PWM3 Stop Register 0xC0F8 R/W
PWM Cycle Count Register 0xC0FA R/W
Table 125. PWM Control Register
Bit # 15 14 13 12 11 10 9 8
Field
PWM
Enable
Reserved Prescale
Select
Mode
Select
Read/Write R/W - - - R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field
PWM 3
Polarity
Select
PWM 2
Polarity
Select
PWM 1
Polarity
Select
PWM 0
Polarity
Select
PWM 3
Enable
PWM 2
Enable
PWM 1
Enable
PWM 0
Enable
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Table 126. Prescaler Select Definition
Prescale Select [11:9] Frequency
000 48.00 MHz
001 24.00 MHz
010 06.00 MHz
011 01.50 MHz
100 375 kHz
101 93.80 kHz
110 23.40 kHz
111 05.90 kHz
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