Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade Support Specification Sheet
Table Of Contents
- EZ-Host Features
- Typical Applications
- Introduction
- Functional Overview
- Interface Descriptions
- USB Interface
- OTG Interface
- External Memory Interface
- General Purpose IO Interface (GPIO)
- UART Interface
- I2C EEPROM Interface
- Serial Peripheral Interface
- High-Speed Serial Interface
- Programmable Pulse/PWM Interface
- Host Port Interface
- IDE Interface
- Charge Pump Interface
- Booster Interface
- Crystal Interface
- Boot Configuration Interface
- Operational Modes
- Power Savings and Reset Description
- Memory Map
- Registers
- Processor Control Registers
- CPU Flags Register [0xC000] [R]
- Bank Register [0xC002] [R/W]
- Hardware Revision Register [0xC004] [R]
- CPU Speed Register [0xC008] [R/W]
- Power Control Register [0xC00A] [R/W]
- Interrupt Enable Register [0xC00E] [R/W]
- Breakpoint Register [0xC014] [R/W]
- USB Diagnostic Register [0xC03C] [R/W]
- Memory Diagnostic Register [0xC03E] [W]
- External Memory Registers
- Timer Registers
- General USB Registers
- USB Host Only Registers
- Host n Control Register [R/W]
- Host n Address Register [R/W]
- Host n Count Register [R/W]
- Host n Endpoint Status Register [R]
- Host n PID Register [W]
- Host n Count Result Register [R]
- Host n Device Address Register [W]
- Host n Interrupt Enable Register [R/W]
- Host n Status Register [R/W]
- Host n SOF/EOP Count Register [R/W]
- Host n SOF/EOP Counter Register [R]
- Host n Frame Register [R]
- USB Device Only Registers
- Device n Endpoint n Control Register [R/W]
- Device n Endpoint n Address Register [R/W]
- Device n Endpoint n Count Register [R/W]
- Device n Endpoint n Status Register [R/W]
- Device n Endpoint n Count Result Register [R/W]
- Device n Port Select Register [R/W]
- Device n Interrupt Enable Register [R/W]
- Device n Address Register [W]
- Device n Status Register [R/W]
- Device n Frame Number Register [R]
- Device n SOF/EOP Count Register [W]
- OTG Control Registers
- GPIO Registers
- IDE Registers
- HSS Registers
- HSS Control Register [0xC070] [R/W]
- HSS Baud Rate Register [0xC072] [R/W]
- HSS Transmit Gap Register [0xC074] [R/W]
- HSS Data Register [0xC076] [R/W]
- HSS Receive Address Register [0xC078] [R/W]
- HSS Receive Counter Register [0xC07A] [R/W]
- HSS Transmit Address Register [0xC07C] [R/W]
- HSS Transmit Counter Register [0xC07E] [R/W]
- HPI Registers
- SPI Registers
- SPI Configuration Register [0xC0C8] [R/W]
- SPI Control Register [0xC0CA] [R/W]
- SPI Interrupt Enable Register [0xC0CC] [R/W]
- SPI Status Register [0xC0CE] [R]
- SPI Interrupt Clear Register [0xC0D0] [W]
- SPI CRC Control Register [0xC0D2] [R/W]
- SPI CRC Value Register [0xC0D4] [R/W]
- SPI Data Register [0xC0D6] [R/W]
- SPI Transmit Address Register [0xC0D8] [R/W]
- SPI Transmit Count Register [0xC0DA] [R/W]
- SPI Receive Address Register [0xC0DC [R/W]
- SPI Receive Count Register [0xC0DE] [R/W]
- UART Registers
- PWM Registers
- Processor Control Registers
- Pin Diagram
- Pin Descriptions
- Absolute Maximum Ratings
- Operating Conditions
- Crystal Requirements (XTALIN, XTALOUT)
- DC Characteristics
- AC Timing Characteristics
- Register Summary
- Ordering Information
- Package Diagrams
- Document History Page
- Sales, Solutions, and Legal Information
CY7C67300
Document #: 38-08015 Rev. *J Page 64 of 99
HPI Status Port [] [HPI: R]
Register Description
The HPI Status Port provides the external host processor with
the MailBox status bits plus several SIE status bits. This register
is not accessible from the on-chip CPU. The additional SIE status
bits are provided to aid external device driver firmware devel-
opment, and are not recommended for applications that do not
have an intimate relationship with the on-chip BIOS.
Reading from the HPI Status Port does not result in a CPU HPI
interface memory access cycle. The external host may continu-
ously poll this register without degrading the CPU or DMA perfor-
mance.
VBUS Flag (Bit 15)
The VBUS Flag bit is a read only bit that indicates whether OTG
VBus is greater than 4.4V. After turning on VBUS, firmware must
wait at least 10 µs before this reading this bit.
1: OTG VBus is greater than 4.4V
0: OTG VBus is less than 4.4V
ID Flag (Bit 14)
The ID Flag bit is a read only bit that indicates the state of the
OTG ID pin.
SOF/EOP2 Flag (Bit 12)
The SOF/EOP2 Flag bit is a read only bit that indicates if a
SOF/EOP interrupt occurs on either Host/Device 2.
1: Interrupt triggered
0: Interrupt did not trigger
SOF/EOP1 Flag (Bit 10)
The SOF/EOP1 Flag bit is a read only bit that indicates if a
SOF/EOP interrupt occurs on either Host/Device 1.
1: Interrupt triggered
0: Interrupt did not trigger
Reset2 Flag (Bit 9)
The Reset2 Flag bit is a read only bit that indicates if a USB
Reset interrupt occurs on either Host/Device 2.
1: Interrupt triggered
0: Interrupt did not trigger
Mailbox In Flag (Bit 8)
The Mailbox In Flag bit is a read only bit that indicates if a
message is ready in the incoming mailbox. This interrupt clears
when the on-chip CPU reads from the HPI Mailbox register.
1: Interrupt triggered
0: Interrupt did not trigger
Resume2 Flag (Bit 7)
The Resume2 Flag bit is a read only bit that indicates if a USB
resume interrupt occurs on either Host/Device 2.
1: Interrupt triggered
0: Interrupt did not trigger
Resume1 Flag (Bit 6)
The Resume1 Flag bit is a read only bit that indicates if a USB
resume interrupt occurs on either Host/Device 1.
1: Interrupt triggered
0: Interrupt did not trigger
SIE2msg (Bit 5)
The SIE2msg Flag bit is a read only bit that indicates if the
CY7C67300 CPU wrote to the SIE2msg register. This bit is
cleared on an HPI read.
1: The SIE2msg register was written by the CY7C67300 CPU
0: The SIE2msg register was not written by the CY7C67300 CPU
SIE1msg (Bit 4)
The SIE1msg Flag bit is a read only bit that indicates if the
CY7C67300 CPU wrote to the SIE1msg register. This bit is
cleared on an HPI read.
1: The SIE1msg register was written by the CY7C67300 CPU
0: The SIE1msg register was not written by the CY7C67300 CPU
Done2 Flag (Bit 3)
In host mode the Done2 Flag bit is a read only bit that indicates
if a host packet done interrupt occurs on Host 2. In device mode
this read only bit indicates if an any of the endpoint interrupts
occur on Device 2. Firmware needs to determine which endpoint
interrupt occurred.
1: Interrupt triggered
0: Interrupt did not trigger
Table 103. HPI Status Port
Bit # 15 14 13 12 11 10 9 8
Field
VBUS
Flag
ID
Flag
Reserved SOF/EOP2
Flag
Reserved SOF/EOP1
Flag
Reset2
Flag
Mailbox In
Flag
Read/Write R R - R - R R R
Default X X X X X X X X
Bit # 7 6 5 4 3 2 1 0
Field
Resume2
Flag
Resume1
Flag
SIE2msg SIE1msg Done2
Flag
Done1
Flag
Reset1
Flag
Mailbox Out
Flag
Read/Write R R R R R R R R
Default X X X X X X X X
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