Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade Support Specification Sheet
Table Of Contents
- EZ-Host Features
- Typical Applications
- Introduction
- Functional Overview
- Interface Descriptions
- USB Interface
- OTG Interface
- External Memory Interface
- General Purpose IO Interface (GPIO)
- UART Interface
- I2C EEPROM Interface
- Serial Peripheral Interface
- High-Speed Serial Interface
- Programmable Pulse/PWM Interface
- Host Port Interface
- IDE Interface
- Charge Pump Interface
- Booster Interface
- Crystal Interface
- Boot Configuration Interface
- Operational Modes
- Power Savings and Reset Description
- Memory Map
- Registers
- Processor Control Registers
- CPU Flags Register [0xC000] [R]
- Bank Register [0xC002] [R/W]
- Hardware Revision Register [0xC004] [R]
- CPU Speed Register [0xC008] [R/W]
- Power Control Register [0xC00A] [R/W]
- Interrupt Enable Register [0xC00E] [R/W]
- Breakpoint Register [0xC014] [R/W]
- USB Diagnostic Register [0xC03C] [R/W]
- Memory Diagnostic Register [0xC03E] [W]
- External Memory Registers
- Timer Registers
- General USB Registers
- USB Host Only Registers
- Host n Control Register [R/W]
- Host n Address Register [R/W]
- Host n Count Register [R/W]
- Host n Endpoint Status Register [R]
- Host n PID Register [W]
- Host n Count Result Register [R]
- Host n Device Address Register [W]
- Host n Interrupt Enable Register [R/W]
- Host n Status Register [R/W]
- Host n SOF/EOP Count Register [R/W]
- Host n SOF/EOP Counter Register [R]
- Host n Frame Register [R]
- USB Device Only Registers
- Device n Endpoint n Control Register [R/W]
- Device n Endpoint n Address Register [R/W]
- Device n Endpoint n Count Register [R/W]
- Device n Endpoint n Status Register [R/W]
- Device n Endpoint n Count Result Register [R/W]
- Device n Port Select Register [R/W]
- Device n Interrupt Enable Register [R/W]
- Device n Address Register [W]
- Device n Status Register [R/W]
- Device n Frame Number Register [R]
- Device n SOF/EOP Count Register [W]
- OTG Control Registers
- GPIO Registers
- IDE Registers
- HSS Registers
- HSS Control Register [0xC070] [R/W]
- HSS Baud Rate Register [0xC072] [R/W]
- HSS Transmit Gap Register [0xC074] [R/W]
- HSS Data Register [0xC076] [R/W]
- HSS Receive Address Register [0xC078] [R/W]
- HSS Receive Counter Register [0xC07A] [R/W]
- HSS Transmit Address Register [0xC07C] [R/W]
- HSS Transmit Counter Register [0xC07E] [R/W]
- HPI Registers
- SPI Registers
- SPI Configuration Register [0xC0C8] [R/W]
- SPI Control Register [0xC0CA] [R/W]
- SPI Interrupt Enable Register [0xC0CC] [R/W]
- SPI Status Register [0xC0CE] [R]
- SPI Interrupt Clear Register [0xC0D0] [W]
- SPI CRC Control Register [0xC0D2] [R/W]
- SPI CRC Value Register [0xC0D4] [R/W]
- SPI Data Register [0xC0D6] [R/W]
- SPI Transmit Address Register [0xC0D8] [R/W]
- SPI Transmit Count Register [0xC0DA] [R/W]
- SPI Receive Address Register [0xC0DC [R/W]
- SPI Receive Count Register [0xC0DE] [R/W]
- UART Registers
- PWM Registers
- Processor Control Registers
- Pin Diagram
- Pin Descriptions
- Absolute Maximum Ratings
- Operating Conditions
- Crystal Requirements (XTALIN, XTALOUT)
- DC Characteristics
- AC Timing Characteristics
- Register Summary
- Ordering Information
- Package Diagrams
- Document History Page
- Sales, Solutions, and Legal Information
CY7C67300
Document #: 38-08015 Rev. *J Page 62 of 99
ID to HPI Enable (Bit 14)
The ID to HPI Enable bit routes the OTG ID interrupt to the HPI
port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
SOF/EOP2 to HPI Enable (Bit 13)
The SOF/EOP2 to HPI Enable bit routes the SOF/EOP2 interrupt
to the HPI port.
1: Route signal to HPI port
0: Do not route signal to HPI port
SOF/EOP2 to CPU Enable (Bit 12)
The SOF/EOP2 to CPU Enable bit routes the SOF/EOP2
interrupt to the on-chip CPU. Since the SOF/EOP2 interrupt can
be routed to both the on-chip CPU and the HPI port, the firmware
must ensure only one of the two (CPU, HPI) resets the interrupt.
1: Route signal to CPU
0: Do not route signal to CPU
SOF/EOP1 to HPI Enable (Bit 11)
The SOF/EOP1 to HPI Enable bit routes the SOF/EOP1 interrupt
to the HPI port.
1: Route signal to HPI port
0: Do not route signal to HPI port
SOF/EOP1 to CPU Enable (Bit 10)
The SOF/EOP1 to CPU Enable bit routes the SOF/EOP1
interrupt to the on-chip CPU. Since the SOF/EOP1 interrupt can
be routed to both the on-chip CPU and the HPI port, the firmware
must ensure only one of the two (CPU, HPI) resets the interrupt.
1: Route signal to CPU
0: Do not route signal to CPU
Reset2 to HPI Enable (Bit 9)
The Reset2 to HPI Enable bit routes the USB Reset interrupt that
occurs on Device 2 to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
HPI Swap 1 Enable (Bit 8)
Both HPI Swap bits (bits 8 and 0) must be set to identical values.
When set to ‘00’, the most significant data byte goes to
HPI_D[15:8] and the least significant byte goes to HPI_D[7:0].
This is the default setting. By setting to ‘11’, the most significant
data byte goes to HPI_D[7:0] and the least significant byte goes
to HPI_D[15:8].
Resume2 to HPI Enable (Bit 7)
The Resume2 to HPI Enable bit routes the USB Resume
interrupt that occurs on Host 2 to the HPI port instead of the
on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
Resume1 to HPI Enable (Bit 6)
The Resume1 to HPI Enable bit routes the USB Resume
interrupt that occurs on Host 1 to the HPI port instead of the
on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
Done2 to HPI Enable (Bit 3)
The Done2 to HPI Enable bit routes the Done interrupt for
Host/Device 2 to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
Done1 to HPI Enable (Bit 2)
The Done1 to HPI Enable bit routes the Done interrupt for
Host/Device 1 to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
Reset1 to HPI Enable (Bit 1)
The Reset1 to HPI Enable bit routes the USB Reset interrupt that
occurs on Device 1 to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port
0: Do not route signal to HPI port
HPI Swap 0 Enable (Bit 0)
Both HPI Swap bits (bits 8 and 0) must be set to identical values.
When set to ‘00’, the most significant data byte goes to
HPI_D[15:8] and the least significant byte goes to HPI_D[7:0].
This is the default setting. By setting to ‘11’, the most significant
data byte goes to HPI_D[7:0] and the least significant byte goes
to HPI_D[15:8].
[+] Feedback