Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade Support Specification Sheet
Table Of Contents
- EZ-Host Features
- Typical Applications
- Introduction
- Functional Overview
- Interface Descriptions
- USB Interface
- OTG Interface
- External Memory Interface
- General Purpose IO Interface (GPIO)
- UART Interface
- I2C EEPROM Interface
- Serial Peripheral Interface
- High-Speed Serial Interface
- Programmable Pulse/PWM Interface
- Host Port Interface
- IDE Interface
- Charge Pump Interface
- Booster Interface
- Crystal Interface
- Boot Configuration Interface
- Operational Modes
- Power Savings and Reset Description
- Memory Map
- Registers
- Processor Control Registers
- CPU Flags Register [0xC000] [R]
- Bank Register [0xC002] [R/W]
- Hardware Revision Register [0xC004] [R]
- CPU Speed Register [0xC008] [R/W]
- Power Control Register [0xC00A] [R/W]
- Interrupt Enable Register [0xC00E] [R/W]
- Breakpoint Register [0xC014] [R/W]
- USB Diagnostic Register [0xC03C] [R/W]
- Memory Diagnostic Register [0xC03E] [W]
- External Memory Registers
- Timer Registers
- General USB Registers
- USB Host Only Registers
- Host n Control Register [R/W]
- Host n Address Register [R/W]
- Host n Count Register [R/W]
- Host n Endpoint Status Register [R]
- Host n PID Register [W]
- Host n Count Result Register [R]
- Host n Device Address Register [W]
- Host n Interrupt Enable Register [R/W]
- Host n Status Register [R/W]
- Host n SOF/EOP Count Register [R/W]
- Host n SOF/EOP Counter Register [R]
- Host n Frame Register [R]
- USB Device Only Registers
- Device n Endpoint n Control Register [R/W]
- Device n Endpoint n Address Register [R/W]
- Device n Endpoint n Count Register [R/W]
- Device n Endpoint n Status Register [R/W]
- Device n Endpoint n Count Result Register [R/W]
- Device n Port Select Register [R/W]
- Device n Interrupt Enable Register [R/W]
- Device n Address Register [W]
- Device n Status Register [R/W]
- Device n Frame Number Register [R]
- Device n SOF/EOP Count Register [W]
- OTG Control Registers
- GPIO Registers
- IDE Registers
- HSS Registers
- HSS Control Register [0xC070] [R/W]
- HSS Baud Rate Register [0xC072] [R/W]
- HSS Transmit Gap Register [0xC074] [R/W]
- HSS Data Register [0xC076] [R/W]
- HSS Receive Address Register [0xC078] [R/W]
- HSS Receive Counter Register [0xC07A] [R/W]
- HSS Transmit Address Register [0xC07C] [R/W]
- HSS Transmit Counter Register [0xC07E] [R/W]
- HPI Registers
- SPI Registers
- SPI Configuration Register [0xC0C8] [R/W]
- SPI Control Register [0xC0CA] [R/W]
- SPI Interrupt Enable Register [0xC0CC] [R/W]
- SPI Status Register [0xC0CE] [R]
- SPI Interrupt Clear Register [0xC0D0] [W]
- SPI CRC Control Register [0xC0D2] [R/W]
- SPI CRC Value Register [0xC0D4] [R/W]
- SPI Data Register [0xC0D6] [R/W]
- SPI Transmit Address Register [0xC0D8] [R/W]
- SPI Transmit Count Register [0xC0DA] [R/W]
- SPI Receive Address Register [0xC0DC [R/W]
- SPI Receive Count Register [0xC0DE] [R/W]
- UART Registers
- PWM Registers
- Processor Control Registers
- Pin Diagram
- Pin Descriptions
- Absolute Maximum Ratings
- Operating Conditions
- Crystal Requirements (XTALIN, XTALOUT)
- DC Characteristics
- AC Timing Characteristics
- Register Summary
- Ordering Information
- Package Diagrams
- Document History Page
- Sales, Solutions, and Legal Information
CY7C67300
Document #: 38-08015 Rev. *J Page 6 of 99
External Memory Interface Pins
External Memory Interface Block Diagrams
Figure 2 illustrates how to connect a 64k × 8 memory array
(SRAM/ROM) to the EZ-Host external memory interface.
Figure 3 illustrates the interface for connecting a 16-bit ROM or
16-bit RAM to the EZ-Host external memory interface. In 16-bit
mode, up to 256K words of external ROM or RAM are supported.
Note that the address lines do not map directly.
Table 6. External Memory Interface Pins
Pin Name Pin Number
nWR 64
nRD 62
nXMEMSEL (optional nCS) 34
nXROMSEL (ROM nCS) 35
nXRAMSEL (RAM nCS) 36
A18 95
A17 96
A16 97
A15 38
A14 33
A13 32
A12 31
A11 30
A10 27
A9 25
A8 24
A7 20
A6 17
A5 8
A4 7
A3 3
A2 2
A1 1
nBEL/A0 99
nBEH 98
D15 67
D14 68
D13 69
D12 70
D11 71
D10 72
D9 73
D8 74
D7 76
D6 77
D5 78
D4 79
D3 80
D2 81
D1 82
D0 83
Figure 2. Interfacing to 64k × 8 Memory Array
Figure 3. Interfacing up to 256k × 16 for External Code/Data
Table 6. External Memory Interface Pins (continued)
Pin Name Pin Number
EZ-Host
CY7C67300
External Memory Array
64K x 8
A[15:0]
nWR
nRD
nXRAMSEL
A[15:0]
WE
OE
CE
D[7:0] D[7:0]
Interfacing to 64K x 8 External Memory Array
EZ-Host
CY7C67300
External Memory Array
Up to 256k x 16
A[18:1]
nBEL
nBEH
nWR
nRD
nXMEMSEL
A[17:0]
BLE
WE
OE
CE
D[15:0] D[15:0]
Up to 256k x 16 External Code/Data (Page Mode)
BHE
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