Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade Support Specification Sheet
Table Of Contents
- EZ-Host Features
- Typical Applications
- Introduction
- Functional Overview
- Interface Descriptions
- USB Interface
- OTG Interface
- External Memory Interface
- General Purpose IO Interface (GPIO)
- UART Interface
- I2C EEPROM Interface
- Serial Peripheral Interface
- High-Speed Serial Interface
- Programmable Pulse/PWM Interface
- Host Port Interface
- IDE Interface
- Charge Pump Interface
- Booster Interface
- Crystal Interface
- Boot Configuration Interface
- Operational Modes
- Power Savings and Reset Description
- Memory Map
- Registers
- Processor Control Registers
- CPU Flags Register [0xC000] [R]
- Bank Register [0xC002] [R/W]
- Hardware Revision Register [0xC004] [R]
- CPU Speed Register [0xC008] [R/W]
- Power Control Register [0xC00A] [R/W]
- Interrupt Enable Register [0xC00E] [R/W]
- Breakpoint Register [0xC014] [R/W]
- USB Diagnostic Register [0xC03C] [R/W]
- Memory Diagnostic Register [0xC03E] [W]
- External Memory Registers
- Timer Registers
- General USB Registers
- USB Host Only Registers
- Host n Control Register [R/W]
- Host n Address Register [R/W]
- Host n Count Register [R/W]
- Host n Endpoint Status Register [R]
- Host n PID Register [W]
- Host n Count Result Register [R]
- Host n Device Address Register [W]
- Host n Interrupt Enable Register [R/W]
- Host n Status Register [R/W]
- Host n SOF/EOP Count Register [R/W]
- Host n SOF/EOP Counter Register [R]
- Host n Frame Register [R]
- USB Device Only Registers
- Device n Endpoint n Control Register [R/W]
- Device n Endpoint n Address Register [R/W]
- Device n Endpoint n Count Register [R/W]
- Device n Endpoint n Status Register [R/W]
- Device n Endpoint n Count Result Register [R/W]
- Device n Port Select Register [R/W]
- Device n Interrupt Enable Register [R/W]
- Device n Address Register [W]
- Device n Status Register [R/W]
- Device n Frame Number Register [R]
- Device n SOF/EOP Count Register [W]
- OTG Control Registers
- GPIO Registers
- IDE Registers
- HSS Registers
- HSS Control Register [0xC070] [R/W]
- HSS Baud Rate Register [0xC072] [R/W]
- HSS Transmit Gap Register [0xC074] [R/W]
- HSS Data Register [0xC076] [R/W]
- HSS Receive Address Register [0xC078] [R/W]
- HSS Receive Counter Register [0xC07A] [R/W]
- HSS Transmit Address Register [0xC07C] [R/W]
- HSS Transmit Counter Register [0xC07E] [R/W]
- HPI Registers
- SPI Registers
- SPI Configuration Register [0xC0C8] [R/W]
- SPI Control Register [0xC0CA] [R/W]
- SPI Interrupt Enable Register [0xC0CC] [R/W]
- SPI Status Register [0xC0CE] [R]
- SPI Interrupt Clear Register [0xC0D0] [W]
- SPI CRC Control Register [0xC0D2] [R/W]
- SPI CRC Value Register [0xC0D4] [R/W]
- SPI Data Register [0xC0D6] [R/W]
- SPI Transmit Address Register [0xC0D8] [R/W]
- SPI Transmit Count Register [0xC0DA] [R/W]
- SPI Receive Address Register [0xC0DC [R/W]
- SPI Receive Count Register [0xC0DE] [R/W]
- UART Registers
- PWM Registers
- Processor Control Registers
- Pin Diagram
- Pin Descriptions
- Absolute Maximum Ratings
- Operating Conditions
- Crystal Requirements (XTALIN, XTALOUT)
- DC Characteristics
- AC Timing Characteristics
- Register Summary
- Ordering Information
- Package Diagrams
- Document History Page
- Sales, Solutions, and Legal Information
CY7C67300
Document #: 38-08015 Rev. *J Page 54 of 99
IDE Stop Address Register [0xC04C] [R/W]
Register Description
The IDE Stop Address register holds the stop address for an IDE
block transfer. This register is byte addressed and IDE block
transfers are 16-bit words, therefore the LSB of the stop address
is ignored. Block transfers begin at IDE Start Address and end
with the final word at IDE Stop Address. When IDE Start Address
equals IDE Stop Address, the block transfer moves one word of
data.
The hardware keeps an internal memory address counter. The
two MSBs of the addresses are not modified by the address
counter. Therefore the IDE Start Address and IDE Stop Address
must reside within the same 16K byte block.
Address (Bits [15:0])
The Address field sets the stop address for an IDE block transfer.
IDE Control Register [0xC04E] [R/W]
Register Description
The IDE Control register controls block transfers in IDE mode.
Direction Select (Bit 3)
The Direction Select bit sets the block mode transfer direction.
1: Data is written to the external device
0: Data is read from the external device
IDE Interrupt Enable (Bit 2)
The IDE Interrupt Enable bit enables or disables the block
transfer done interrupt. When enabled, the Done Flag is sent to
the CPU as cpuide_intr interrupt. When disabled, the cpuide_intr
is set LOW.
1: Enable block transfer done interrupt
0: Disable block transfer done interrupt
Done Flag (Bit 1)
The Done Flag bit is automatically set to ‘1’ by hardware when a
block transfer is complete. The CPU clears this bit by writing a
‘0’ to it. When IDE Interrupt Enable is set this bit generates the
signal for the cpuide_intr interrupt.
1: Block transfer is complete
0: Clears IDE Done Flag
IDE Enable (Bit 0)
The IDE Enable bit starts a block transfer. It is reset to ‘0’ when
the block transfer is complete
1: Start block transfer
0: Block transfer complete
Reserved
Write all reserved bits with ’0’.
Table 86. IDE Stop Address Register
Bit # 15 14 13 12 11 10 9 8
Field Address...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Address
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Table 87. IDE Control Register
Bit # 15 14 13 12 11 10 9 8
Field Reserved...
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field
...Reserved Direction
Select
IDE
Interrupt
Enable
Done
Flag
IDE
Enable
Read/Write - - - - R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
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