Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade Support Specification Sheet
Table Of Contents
- EZ-Host Features
- Typical Applications
- Introduction
- Functional Overview
- Interface Descriptions
- USB Interface
- OTG Interface
- External Memory Interface
- General Purpose IO Interface (GPIO)
- UART Interface
- I2C EEPROM Interface
- Serial Peripheral Interface
- High-Speed Serial Interface
- Programmable Pulse/PWM Interface
- Host Port Interface
- IDE Interface
- Charge Pump Interface
- Booster Interface
- Crystal Interface
- Boot Configuration Interface
- Operational Modes
- Power Savings and Reset Description
- Memory Map
- Registers
- Processor Control Registers
- CPU Flags Register [0xC000] [R]
- Bank Register [0xC002] [R/W]
- Hardware Revision Register [0xC004] [R]
- CPU Speed Register [0xC008] [R/W]
- Power Control Register [0xC00A] [R/W]
- Interrupt Enable Register [0xC00E] [R/W]
- Breakpoint Register [0xC014] [R/W]
- USB Diagnostic Register [0xC03C] [R/W]
- Memory Diagnostic Register [0xC03E] [W]
- External Memory Registers
- Timer Registers
- General USB Registers
- USB Host Only Registers
- Host n Control Register [R/W]
- Host n Address Register [R/W]
- Host n Count Register [R/W]
- Host n Endpoint Status Register [R]
- Host n PID Register [W]
- Host n Count Result Register [R]
- Host n Device Address Register [W]
- Host n Interrupt Enable Register [R/W]
- Host n Status Register [R/W]
- Host n SOF/EOP Count Register [R/W]
- Host n SOF/EOP Counter Register [R]
- Host n Frame Register [R]
- USB Device Only Registers
- Device n Endpoint n Control Register [R/W]
- Device n Endpoint n Address Register [R/W]
- Device n Endpoint n Count Register [R/W]
- Device n Endpoint n Status Register [R/W]
- Device n Endpoint n Count Result Register [R/W]
- Device n Port Select Register [R/W]
- Device n Interrupt Enable Register [R/W]
- Device n Address Register [W]
- Device n Status Register [R/W]
- Device n Frame Number Register [R]
- Device n SOF/EOP Count Register [W]
- OTG Control Registers
- GPIO Registers
- IDE Registers
- HSS Registers
- HSS Control Register [0xC070] [R/W]
- HSS Baud Rate Register [0xC072] [R/W]
- HSS Transmit Gap Register [0xC074] [R/W]
- HSS Data Register [0xC076] [R/W]
- HSS Receive Address Register [0xC078] [R/W]
- HSS Receive Counter Register [0xC07A] [R/W]
- HSS Transmit Address Register [0xC07C] [R/W]
- HSS Transmit Counter Register [0xC07E] [R/W]
- HPI Registers
- SPI Registers
- SPI Configuration Register [0xC0C8] [R/W]
- SPI Control Register [0xC0CA] [R/W]
- SPI Interrupt Enable Register [0xC0CC] [R/W]
- SPI Status Register [0xC0CE] [R]
- SPI Interrupt Clear Register [0xC0D0] [W]
- SPI CRC Control Register [0xC0D2] [R/W]
- SPI CRC Value Register [0xC0D4] [R/W]
- SPI Data Register [0xC0D6] [R/W]
- SPI Transmit Address Register [0xC0D8] [R/W]
- SPI Transmit Count Register [0xC0DA] [R/W]
- SPI Receive Address Register [0xC0DC [R/W]
- SPI Receive Count Register [0xC0DE] [R/W]
- UART Registers
- PWM Registers
- Processor Control Registers
- Pin Diagram
- Pin Descriptions
- Absolute Maximum Ratings
- Operating Conditions
- Crystal Requirements (XTALIN, XTALOUT)
- DC Characteristics
- AC Timing Characteristics
- Register Summary
- Ordering Information
- Package Diagrams
- Document History Page
- Sales, Solutions, and Legal Information
CY7C67300
Document #: 38-08015 Rev. *J Page 52 of 99
GPIO n Direction Register [R/W]
■ GPIO 0 Direction Register 0xC022
■ GPIO 1 Direction Register 0xC028
Register Description
The GPIO n Direction register controls the direction of the GPIO
data pins (input/output). The GPIO 0 Direction register controls
GPIO15 to GPIO0 while the GPIO 1 Direction register controls
GPIO31 to GPIO16.
Direction Select (Bits [15:0])
The Direction Select field[15:0] configures the corresponding
GPIO15–0 or GPIO31–16 pins as either input or output. When
any bit of this register is set to ‘1’, the corresponding GPIO data
pin becomes an output. When any bit of this register is set to ‘0’,
the corresponding GPIO data pin becomes an input.
IDE Registers
In addition to the standard IDE PIO Port registers, there are four
registers dedicated to IDE operation. These registers are
covered in this section and summarized in Table 82.
IDE Mode Register [0xC048] [R/ W]
Register Description
The IDE Mode register allows the selection of IDE PIO Modes 0,
1, 2, 3, or 4. The default setting is zero which means IDE PIO
Mode 0.
Mode Select (Bits [2:0])
The Mode Select field sets PIO Mode 0 to 4 in IDE mode. Refer
to Table 84 on page 53 for a definition of this field.
Table 81. GPIO n Direction Register
Bit # 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8
Field Direction Select...
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0
Field ...Direction Select
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
Table 82. IDE Registers
Register Name Address R/W
IDE Mode Register 0xC048 R/W
IDE Start Address Register 0xC04A R/W
IDE Stop Address Register 0xC04C R/W
IDE Control Register 0xC04E R/W
IDE PIO Port Registers 0xC050-0xC06F R/W
Table 83. IDE Mode Register
Bit # 15 14 13 12 11 10 9 8
Field Reserved...
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Reserved Mode Select
Read/Write - - - - R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
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