Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade Support Specification Sheet
Table Of Contents
- EZ-Host Features
- Typical Applications
- Introduction
- Functional Overview
- Interface Descriptions
- USB Interface
- OTG Interface
- External Memory Interface
- General Purpose IO Interface (GPIO)
- UART Interface
- I2C EEPROM Interface
- Serial Peripheral Interface
- High-Speed Serial Interface
- Programmable Pulse/PWM Interface
- Host Port Interface
- IDE Interface
- Charge Pump Interface
- Booster Interface
- Crystal Interface
- Boot Configuration Interface
- Operational Modes
- Power Savings and Reset Description
- Memory Map
- Registers
- Processor Control Registers
- CPU Flags Register [0xC000] [R]
- Bank Register [0xC002] [R/W]
- Hardware Revision Register [0xC004] [R]
- CPU Speed Register [0xC008] [R/W]
- Power Control Register [0xC00A] [R/W]
- Interrupt Enable Register [0xC00E] [R/W]
- Breakpoint Register [0xC014] [R/W]
- USB Diagnostic Register [0xC03C] [R/W]
- Memory Diagnostic Register [0xC03E] [W]
- External Memory Registers
- Timer Registers
- General USB Registers
- USB Host Only Registers
- Host n Control Register [R/W]
- Host n Address Register [R/W]
- Host n Count Register [R/W]
- Host n Endpoint Status Register [R]
- Host n PID Register [W]
- Host n Count Result Register [R]
- Host n Device Address Register [W]
- Host n Interrupt Enable Register [R/W]
- Host n Status Register [R/W]
- Host n SOF/EOP Count Register [R/W]
- Host n SOF/EOP Counter Register [R]
- Host n Frame Register [R]
- USB Device Only Registers
- Device n Endpoint n Control Register [R/W]
- Device n Endpoint n Address Register [R/W]
- Device n Endpoint n Count Register [R/W]
- Device n Endpoint n Status Register [R/W]
- Device n Endpoint n Count Result Register [R/W]
- Device n Port Select Register [R/W]
- Device n Interrupt Enable Register [R/W]
- Device n Address Register [W]
- Device n Status Register [R/W]
- Device n Frame Number Register [R]
- Device n SOF/EOP Count Register [W]
- OTG Control Registers
- GPIO Registers
- IDE Registers
- HSS Registers
- HSS Control Register [0xC070] [R/W]
- HSS Baud Rate Register [0xC072] [R/W]
- HSS Transmit Gap Register [0xC074] [R/W]
- HSS Data Register [0xC076] [R/W]
- HSS Receive Address Register [0xC078] [R/W]
- HSS Receive Counter Register [0xC07A] [R/W]
- HSS Transmit Address Register [0xC07C] [R/W]
- HSS Transmit Counter Register [0xC07E] [R/W]
- HPI Registers
- SPI Registers
- SPI Configuration Register [0xC0C8] [R/W]
- SPI Control Register [0xC0CA] [R/W]
- SPI Interrupt Enable Register [0xC0CC] [R/W]
- SPI Status Register [0xC0CE] [R]
- SPI Interrupt Clear Register [0xC0D0] [W]
- SPI CRC Control Register [0xC0D2] [R/W]
- SPI CRC Value Register [0xC0D4] [R/W]
- SPI Data Register [0xC0D6] [R/W]
- SPI Transmit Address Register [0xC0D8] [R/W]
- SPI Transmit Count Register [0xC0DA] [R/W]
- SPI Receive Address Register [0xC0DC [R/W]
- SPI Receive Count Register [0xC0DE] [R/W]
- UART Registers
- PWM Registers
- Processor Control Registers
- Pin Diagram
- Pin Descriptions
- Absolute Maximum Ratings
- Operating Conditions
- Crystal Requirements (XTALIN, XTALOUT)
- DC Characteristics
- AC Timing Characteristics
- Register Summary
- Ordering Information
- Package Diagrams
- Document History Page
- Sales, Solutions, and Legal Information
CY7C67300
Document #: 38-08015 Rev. *J Page 49 of 99
Receive Disable (Bit 12)
The Receive Disable bit enables or powers down (disables) the
OTG receiver section.
1: OTG receiver powered down and disabled
0: OTG receiver enabled
Charge Pump Enable (Bit 11)
The Charge Pump Enable bit enables or disables the OTG VBus
charge pump.
1: OTG VBus charge pump enabled
0: OTG VBus charge pump disabled
VBUS Discharge Enable (Bit 10)
The VBUS Discharge Enable bit enables or disables a 2K ohm
discharge pull down resistor onto OTG VBus.
1: 2K ohm pull down resistor enabled
0: 2K ohm pull down resistor disabled
D+ Pull-up Enable (Bit 9)
The D+ Pull-up Enable bit enables or disables a pull up resistor
on the OTG D+ data line.
1: OTG D+ dataline pull up resistor enabled
0: OTG D+ dataline pull up resistor disabled
D– Pull-up Enable (Bit 8)
The D– Pull-up Enable bit enables or disables a pull up resistor
on the OTG D– data line.
1: OTG D– dataline pull up resistor enabled
0: OTG D– dataline pull up resistor disabled
D+ Pull-down Enable (Bit 7)
The D+ Pull-down Enable bit enables or disables a pull down
resistor on the OTG D+ data line.
1: OTG D+ dataline pull down resistor enabled
0: OTG D+ dataline pull down resistor disabled
D– Pull-down Enable (Bit 6)
The D– Pull-down Enable bit enables or disables a pull down
resistor on the OTG D– data line.
1: OTG D– dataline pull down resistor enabled
0: OTG D– dataline pull down resistor disabled
OTG Data Status (Bit 2)
The OTG Data Status bit is a read only bit and indicates the TTL
logic state of the OTG VBus pin.
1: OTG VBus is greater then 2.4V
0: OTG VBus is less then 0.8V
ID Status (Bit 1)
The ID Status bit is a read only bit that indicates the state of the
OTG ID pin on Port A.
1: OTG ID Pin is not connected directly to ground (>10K ohm)
0: OTG ID Pin is connected directly ground (< 10 ohm)
VBUS Valid Flag (Bit 0)
The VBUS Valid Flag bit indicates whether OTG VBus is greater
then 4.4V. After turning on VBUS, firmware must wait at least 10
µs before this reading this bit.
1: OTG VBus is greater then 4.4V
0: OTG VBus is less then 4.4V
Reserved
Write all reserved bits with ’0’.
GPIO Registers
There are seven registers dedicated for GPIO operations. These
seven registers are covered in this section and summarized in
Table 76.
Table 76. GPIO Registers
Register Name Address R/W
GPIO Control Register 0xC006 R/W
GPIO0 Output Data Register 0xC01E R/W
GPIO0 Input Data Register 0xC020 R
GPIO0 Direction Register 0xC022 R/W
GPIO1 Output Data Register 0xC024 R/W
GPIO1 Input Data Register 0xC026 R
GPIO1 Direction Register 0xC028 R/W
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