Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade Support Specification Sheet
Table Of Contents
- EZ-Host Features
- Typical Applications
- Introduction
- Functional Overview
- Interface Descriptions
- USB Interface
- OTG Interface
- External Memory Interface
- General Purpose IO Interface (GPIO)
- UART Interface
- I2C EEPROM Interface
- Serial Peripheral Interface
- High-Speed Serial Interface
- Programmable Pulse/PWM Interface
- Host Port Interface
- IDE Interface
- Charge Pump Interface
- Booster Interface
- Crystal Interface
- Boot Configuration Interface
- Operational Modes
- Power Savings and Reset Description
- Memory Map
- Registers
- Processor Control Registers
- CPU Flags Register [0xC000] [R]
- Bank Register [0xC002] [R/W]
- Hardware Revision Register [0xC004] [R]
- CPU Speed Register [0xC008] [R/W]
- Power Control Register [0xC00A] [R/W]
- Interrupt Enable Register [0xC00E] [R/W]
- Breakpoint Register [0xC014] [R/W]
- USB Diagnostic Register [0xC03C] [R/W]
- Memory Diagnostic Register [0xC03E] [W]
- External Memory Registers
- Timer Registers
- General USB Registers
- USB Host Only Registers
- Host n Control Register [R/W]
- Host n Address Register [R/W]
- Host n Count Register [R/W]
- Host n Endpoint Status Register [R]
- Host n PID Register [W]
- Host n Count Result Register [R]
- Host n Device Address Register [W]
- Host n Interrupt Enable Register [R/W]
- Host n Status Register [R/W]
- Host n SOF/EOP Count Register [R/W]
- Host n SOF/EOP Counter Register [R]
- Host n Frame Register [R]
- USB Device Only Registers
- Device n Endpoint n Control Register [R/W]
- Device n Endpoint n Address Register [R/W]
- Device n Endpoint n Count Register [R/W]
- Device n Endpoint n Status Register [R/W]
- Device n Endpoint n Count Result Register [R/W]
- Device n Port Select Register [R/W]
- Device n Interrupt Enable Register [R/W]
- Device n Address Register [W]
- Device n Status Register [R/W]
- Device n Frame Number Register [R]
- Device n SOF/EOP Count Register [W]
- OTG Control Registers
- GPIO Registers
- IDE Registers
- HSS Registers
- HSS Control Register [0xC070] [R/W]
- HSS Baud Rate Register [0xC072] [R/W]
- HSS Transmit Gap Register [0xC074] [R/W]
- HSS Data Register [0xC076] [R/W]
- HSS Receive Address Register [0xC078] [R/W]
- HSS Receive Counter Register [0xC07A] [R/W]
- HSS Transmit Address Register [0xC07C] [R/W]
- HSS Transmit Counter Register [0xC07E] [R/W]
- HPI Registers
- SPI Registers
- SPI Configuration Register [0xC0C8] [R/W]
- SPI Control Register [0xC0CA] [R/W]
- SPI Interrupt Enable Register [0xC0CC] [R/W]
- SPI Status Register [0xC0CE] [R]
- SPI Interrupt Clear Register [0xC0D0] [W]
- SPI CRC Control Register [0xC0D2] [R/W]
- SPI CRC Value Register [0xC0D4] [R/W]
- SPI Data Register [0xC0D6] [R/W]
- SPI Transmit Address Register [0xC0D8] [R/W]
- SPI Transmit Count Register [0xC0DA] [R/W]
- SPI Receive Address Register [0xC0DC [R/W]
- SPI Receive Count Register [0xC0DE] [R/W]
- UART Registers
- PWM Registers
- Processor Control Registers
- Pin Diagram
- Pin Descriptions
- Absolute Maximum Ratings
- Operating Conditions
- Crystal Requirements (XTALIN, XTALOUT)
- DC Characteristics
- AC Timing Characteristics
- Register Summary
- Ordering Information
- Package Diagrams
- Document History Page
- Sales, Solutions, and Legal Information
CY7C67300
Document #: 38-08015 Rev. *J Page 43 of 99
The Device n Endpoint n Count Result register is a
memory-based register that must be initialized to 0x0000 before
USB Device operations are initiated. After initialization, do not
write to this register again.
Result (Bits [15:0])
The Result field contains the differences in bytes between the
received packet and the value specified in the Device n Endpoint
n Count register. If an overflow condition occurs, Result [15:10]
is set to ‘111111’, a 2’s complement value indicating the
additional byte count of the received packet. If an underflow
condition occurs, Result [15:0] indicates the excess bytes count
(number of bytes not used).
Reserved
Write all reserved bits with ‘0’.
Device n Port Select Register [R/W]
■ Device n Port Select Register 0xC084
■ Device n Port Select Register 0xC0A4
Register Description
The Device n Port Select register selects either port A or port B
for the static device port.
Port Select (Bit 14)
The Port Select bit selects which of the two ports is enabled.
1: Port 1B or Port 2B is enabled
0: Port 1A or Port 2A is enabled
Device n Interrupt Enable Register [R/W]
■ Device 1 Interrupt Enable Register 0xC08C
■ Device 2 Interrupt Enable Register 0xC0AC
Register Description
The Device n Interrupt Enable register provides control over
device related interrupts including eight different endpoint inter-
rupts.
VBUS Interrupt Enable (Bit 15)
The VBUS Interrupt Enable bit enables or disables the OTG
VBUS interrupt. When enabled, this interrupt triggers on both the
rising and falling edge of VBUS at the 4.4V status (only
Table 68. Device n Port Select Register
Bit # 15 14 13 12 11 10 9 8
Field
Reserved Port
Select
Reserved...
Read/Write - R/W - - - - - -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field ...Reserved
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0
Table 69. Device n Interrupt Enable Register
Bit # 15 14 13 12 11 10 9 8
Field
VBUS
Interrupt
Enable
ID Interrupt
Enable
Reserved SOF/EOP
Timeout
Interrupt
Enable
Reserved SOF/EOP
Interrupt
Enable
Reset
Interrupt
Enable
Read/Write R/W R/W - - R/W - R/W R/W
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field
EP7 Interrupt
Enable
EP6 Interrupt
Enable
EP5 Interrupt
Enable
EP4 Interrupt
Enable
EP3 Interrupt
Enable
EP2 Interrupt
Enable
EP1 Interrupt
Enable
EP0 Interrupt
Enable
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0
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