Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade Support Specification Sheet
Table Of Contents
- EZ-Host Features
- Typical Applications
- Introduction
- Functional Overview
- Interface Descriptions
- USB Interface
- OTG Interface
- External Memory Interface
- General Purpose IO Interface (GPIO)
- UART Interface
- I2C EEPROM Interface
- Serial Peripheral Interface
- High-Speed Serial Interface
- Programmable Pulse/PWM Interface
- Host Port Interface
- IDE Interface
- Charge Pump Interface
- Booster Interface
- Crystal Interface
- Boot Configuration Interface
- Operational Modes
- Power Savings and Reset Description
- Memory Map
- Registers
- Processor Control Registers
- CPU Flags Register [0xC000] [R]
- Bank Register [0xC002] [R/W]
- Hardware Revision Register [0xC004] [R]
- CPU Speed Register [0xC008] [R/W]
- Power Control Register [0xC00A] [R/W]
- Interrupt Enable Register [0xC00E] [R/W]
- Breakpoint Register [0xC014] [R/W]
- USB Diagnostic Register [0xC03C] [R/W]
- Memory Diagnostic Register [0xC03E] [W]
- External Memory Registers
- Timer Registers
- General USB Registers
- USB Host Only Registers
- Host n Control Register [R/W]
- Host n Address Register [R/W]
- Host n Count Register [R/W]
- Host n Endpoint Status Register [R]
- Host n PID Register [W]
- Host n Count Result Register [R]
- Host n Device Address Register [W]
- Host n Interrupt Enable Register [R/W]
- Host n Status Register [R/W]
- Host n SOF/EOP Count Register [R/W]
- Host n SOF/EOP Counter Register [R]
- Host n Frame Register [R]
- USB Device Only Registers
- Device n Endpoint n Control Register [R/W]
- Device n Endpoint n Address Register [R/W]
- Device n Endpoint n Count Register [R/W]
- Device n Endpoint n Status Register [R/W]
- Device n Endpoint n Count Result Register [R/W]
- Device n Port Select Register [R/W]
- Device n Interrupt Enable Register [R/W]
- Device n Address Register [W]
- Device n Status Register [R/W]
- Device n Frame Number Register [R]
- Device n SOF/EOP Count Register [W]
- OTG Control Registers
- GPIO Registers
- IDE Registers
- HSS Registers
- HSS Control Register [0xC070] [R/W]
- HSS Baud Rate Register [0xC072] [R/W]
- HSS Transmit Gap Register [0xC074] [R/W]
- HSS Data Register [0xC076] [R/W]
- HSS Receive Address Register [0xC078] [R/W]
- HSS Receive Counter Register [0xC07A] [R/W]
- HSS Transmit Address Register [0xC07C] [R/W]
- HSS Transmit Counter Register [0xC07E] [R/W]
- HPI Registers
- SPI Registers
- SPI Configuration Register [0xC0C8] [R/W]
- SPI Control Register [0xC0CA] [R/W]
- SPI Interrupt Enable Register [0xC0CC] [R/W]
- SPI Status Register [0xC0CE] [R]
- SPI Interrupt Clear Register [0xC0D0] [W]
- SPI CRC Control Register [0xC0D2] [R/W]
- SPI CRC Value Register [0xC0D4] [R/W]
- SPI Data Register [0xC0D6] [R/W]
- SPI Transmit Address Register [0xC0D8] [R/W]
- SPI Transmit Count Register [0xC0DA] [R/W]
- SPI Receive Address Register [0xC0DC [R/W]
- SPI Receive Count Register [0xC0DE] [R/W]
- UART Registers
- PWM Registers
- Processor Control Registers
- Pin Diagram
- Pin Descriptions
- Absolute Maximum Ratings
- Operating Conditions
- Crystal Requirements (XTALIN, XTALOUT)
- DC Characteristics
- AC Timing Characteristics
- Register Summary
- Ordering Information
- Package Diagrams
- Document History Page
- Sales, Solutions, and Legal Information
CY7C67300
Document #: 38-08015 Rev. *J Page 41 of 99
Device n Endpoint n Status Register [R/W]
■ Device n Endpoint 0 Status Register [Device 1: 0x0206 Device 2: 0x0286]
■ Device n Endpoint 1 Status Register [Device 1: 0x0216 Device 2: 0x0296]
■ Device n Endpoint 2 Status Register [Device 1: 0x0226 Device 2: 0x02A6]
■ Device n Endpoint 3 Status Register [Device 1: 0x0236 Device 2: 0x02B6]
■ Device n Endpoint 4 Status Register [Device 1: 0x0246 Device 2: 0x02C6]
■ Device n Endpoint 5 Status Register [Device 1: 0x0256 Device 2: 0x02D6]
■ Device n Endpoint 6 Status Register [Device 1: 0x0266 Device 2: 0x02E6]
■ Device n Endpoint 7 Status Register [Device 1: 0x0276 Device 2: 0x02F6]
Register Description
The Device n Endpoint n Status register provides packet status
information for the last transaction received or transmitted. This
register is updated in hardware and does not need to be cleared
by firmware. There are a total of eight endpoints for each of the
two ports. All endpoints have the same definition for their Device
n Endpoint n Status register.
The Device n Endpoint n Status register is a memory based
register that must be initialized to 0x0000 before USB Device
operations are initiated. After initialization, do not write to this
register again.
Overflow Flag (Bit 11)
The Overflow Flag bit indicates that the received data in the last
data transaction exceeded the maximum length specified in the
Device n Endpoint n Count register. The Overflow Flag must be
checked in response to a Length Exception signified by the
Length Exception Flag set to ‘1’.
1: Overflow condition occurred
0: Overflow condition did not occur
Underflow Flag (Bit 10)
The Underflow Flag bit indicates that the received data in the last
data transaction was less then the maximum length specified in
the Device n Endpoint n Count register. The Underflow Flag must
be checked in response to a Length Exception signified by the
Length Exception Flag set to ‘1’.
1: Underflow condition occurred
0: Underflow condition did not occur
OUT Exception Flag (Bit 9)
The OUT Exception Flag bit indicates when the device received
an OUT packet when armed for an IN.
1: Received OUT when armed for IN
0: Received IN when armed for IN
IN Exception Flag (Bit 8)
The IN Exception Flag bit indicates when the device received an
IN packet when armed for an OUT.
1: Received IN when armed for OUT
0: Received OUT when armed for OUT
Stall Flag (Bit 7)
The Stall Flag bit indicates that a Stall packet was sent to the
host.
1: Stall packet was sent to the host
0: Stall packet was not sent
NAK Flag (Bit 6)
The NAK Flag bit indicates that a NAK packet was sent to the
host.
1: NAK packet was sent to the host
0: NAK packet was not sent
Length Exception Flag (Bit 5)
The Length Exception Flag bit indicates the received data in the
data stage of the last transaction does not equal the maximum
Endpoint Count specified in the Device n Endpoint n Count
register. A Length Exception can either mean an overflow or
Table 66. Device n Endpoint n Status Register
Bit # 15 14 13 12 11 10 9 8
Field
Reserved Overflow
Flag
Underflow
Flag
OUT
Exception Flag
IN
Exception Flag
Read/Write - - - - R/W R/W R/W R/W
Default X X X X X X X X
Bit # 7 6 5 4 3 2 1 0
Field
Stall
Flag
NAK
Flag
Length
Exception Flag
Setup
Flag
Sequence
Flag
Timeout
Flag
Error
Flag
ACK
Flag
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default X X X X X X X X
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