Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade Support Specification Sheet
Table Of Contents
- EZ-Host Features
- Typical Applications
- Introduction
- Functional Overview
- Interface Descriptions
- USB Interface
- OTG Interface
- External Memory Interface
- General Purpose IO Interface (GPIO)
- UART Interface
- I2C EEPROM Interface
- Serial Peripheral Interface
- High-Speed Serial Interface
- Programmable Pulse/PWM Interface
- Host Port Interface
- IDE Interface
- Charge Pump Interface
- Booster Interface
- Crystal Interface
- Boot Configuration Interface
- Operational Modes
- Power Savings and Reset Description
- Memory Map
- Registers
- Processor Control Registers
- CPU Flags Register [0xC000] [R]
- Bank Register [0xC002] [R/W]
- Hardware Revision Register [0xC004] [R]
- CPU Speed Register [0xC008] [R/W]
- Power Control Register [0xC00A] [R/W]
- Interrupt Enable Register [0xC00E] [R/W]
- Breakpoint Register [0xC014] [R/W]
- USB Diagnostic Register [0xC03C] [R/W]
- Memory Diagnostic Register [0xC03E] [W]
- External Memory Registers
- Timer Registers
- General USB Registers
- USB Host Only Registers
- Host n Control Register [R/W]
- Host n Address Register [R/W]
- Host n Count Register [R/W]
- Host n Endpoint Status Register [R]
- Host n PID Register [W]
- Host n Count Result Register [R]
- Host n Device Address Register [W]
- Host n Interrupt Enable Register [R/W]
- Host n Status Register [R/W]
- Host n SOF/EOP Count Register [R/W]
- Host n SOF/EOP Counter Register [R]
- Host n Frame Register [R]
- USB Device Only Registers
- Device n Endpoint n Control Register [R/W]
- Device n Endpoint n Address Register [R/W]
- Device n Endpoint n Count Register [R/W]
- Device n Endpoint n Status Register [R/W]
- Device n Endpoint n Count Result Register [R/W]
- Device n Port Select Register [R/W]
- Device n Interrupt Enable Register [R/W]
- Device n Address Register [W]
- Device n Status Register [R/W]
- Device n Frame Number Register [R]
- Device n SOF/EOP Count Register [W]
- OTG Control Registers
- GPIO Registers
- IDE Registers
- HSS Registers
- HSS Control Register [0xC070] [R/W]
- HSS Baud Rate Register [0xC072] [R/W]
- HSS Transmit Gap Register [0xC074] [R/W]
- HSS Data Register [0xC076] [R/W]
- HSS Receive Address Register [0xC078] [R/W]
- HSS Receive Counter Register [0xC07A] [R/W]
- HSS Transmit Address Register [0xC07C] [R/W]
- HSS Transmit Counter Register [0xC07E] [R/W]
- HPI Registers
- SPI Registers
- SPI Configuration Register [0xC0C8] [R/W]
- SPI Control Register [0xC0CA] [R/W]
- SPI Interrupt Enable Register [0xC0CC] [R/W]
- SPI Status Register [0xC0CE] [R]
- SPI Interrupt Clear Register [0xC0D0] [W]
- SPI CRC Control Register [0xC0D2] [R/W]
- SPI CRC Value Register [0xC0D4] [R/W]
- SPI Data Register [0xC0D6] [R/W]
- SPI Transmit Address Register [0xC0D8] [R/W]
- SPI Transmit Count Register [0xC0DA] [R/W]
- SPI Receive Address Register [0xC0DC [R/W]
- SPI Receive Count Register [0xC0DE] [R/W]
- UART Registers
- PWM Registers
- Processor Control Registers
- Pin Diagram
- Pin Descriptions
- Absolute Maximum Ratings
- Operating Conditions
- Crystal Requirements (XTALIN, XTALOUT)
- DC Characteristics
- AC Timing Characteristics
- Register Summary
- Ordering Information
- Package Diagrams
- Document History Page
- Sales, Solutions, and Legal Information
CY7C67300
Document #: 38-08015 Rev. *J Page 36 of 99
SOF/EOP Interrupt Flag (Bit 9)
The SOF/EOP Interrupt Flag bit indicates the status of the
SOF/EOP Timer interrupt. This bit triggers ‘1’ when the
SOF/EOP timer expires.
1: Interrupt triggered
0: Interrupt did not trigger
Port B Wake Interrupt Flag (Bit 7)
The Port B Wake Interrupt Flag bit indicates remote wakeup on
PortB.
1: Interrupt triggered
0: Interrupt did not trigger
Port A Wake Interrupt Flag (Bit 6)
The Port A Wake Interrupt Flag bit indicates remote wakeup on
PortA.
1: Interrupt triggered
0: Interrupt did not trigger
Port B Connect Change Interrupt Flag (Bit 5)
The Port B Connect Change Interrupt Flag bit indicates the
status of the Connect Change interrupt on Port B. This bit
triggers ‘1’ on either a rising edge or falling edge of a USB Reset
condition (device inserted or removed). Together with the Port B
SE0 Status bit, it can be determined whether a device was
inserted or removed.
1: Interrupt triggered
0: Interrupt did not trigger
Port A Connect Change Interrupt Flag (Bit 4)
The Port A Connect Change Interrupt Flag bit indicates the
status of the Connect Change interrupt on Port A. This bit
triggers ‘1’ on either a rising edge or falling edge of a USB Reset
condition (device inserted or removed). Together with the Port A
SE0 Status bit, it can be determined whether a device was
inserted or removed.
1: Interrupt triggered
0: Interrupt did not trigger
Port B SE0 Status (Bit 3)
The Port B SE0 Status bit indicates if Port B is in a SE0 state or
not. Together with the Port B Connect Change Interrupt Flag bit,
it can be determined whether a device was inserted (non-SE0
condition) or removed (SE0 condition).
1: SE0 condition
0: Non-SE0 condition
Port A SE0 Status (Bit 2)
The Port A SE0 Status bit indicates if Port A is in a SE0 state or
not. Together with the Port A Connect change Interrupt Flag bit,
it can be determined whether a device was inserted (non-SE0
condition) or removed (SE0 condition).
1: SE0 condition
0: Non-SE0 condition
Done Interrupt Flag (Bit 0)
The Done Interrupt Flag bit indicates the status of the USB
Transfer Done interrupt. The USB Transfer Done triggers when
either the host responds with an ACK, or a device responds with
any of the following: ACK, NAK, STALL, or Timeout. This
interrupt is used for both Port A and Port B.
1: Interrupt triggered
0: Interrupt did not trigger
Host n SOF/EOP Count Register [R/W]
■ Host 1 SOF/EOP Count Register 0xC092
■ Host 2 SOF/EOP Count Register 0xC0B2
Register Description
The Host n SOF/EOP Count register contains the SOF/EOP
Count Value that is loaded into the SOF/EOP counter. This value
is loaded each time the SOF/EOP counter counts down to zero.
The default value set in this register at power up is 0x2EE0 which
generates a 1 ms time frame. The SOF/EOP counter is a down
counter decremented at a 12 MHz rate. When this register is
read, the value returned is the programmed SOF/EOP count
value.
Count (Bits [13:0])
The Count field sets the SOF/EOP counter duration.
Reserved
Write all reserved bits with ’0’.
Table 59. Host n SOF/EOP Count Register
Bit # 15 14 13 12 11 10 9 8
Field Reserved Count...
Read/Write - - R/W R/W R/W R/W R/W R/W
Default 0 0 1 0 1 1 1 0
Bit # 7 6 5 4 3 2 1 0
Field ...Count
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default 1 1 1 0 0 0 0 0
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