Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade Support Specification Sheet
Table Of Contents
- EZ-Host Features
- Typical Applications
- Introduction
- Functional Overview
- Interface Descriptions
- USB Interface
- OTG Interface
- External Memory Interface
- General Purpose IO Interface (GPIO)
- UART Interface
- I2C EEPROM Interface
- Serial Peripheral Interface
- High-Speed Serial Interface
- Programmable Pulse/PWM Interface
- Host Port Interface
- IDE Interface
- Charge Pump Interface
- Booster Interface
- Crystal Interface
- Boot Configuration Interface
- Operational Modes
- Power Savings and Reset Description
- Memory Map
- Registers
- Processor Control Registers
- CPU Flags Register [0xC000] [R]
- Bank Register [0xC002] [R/W]
- Hardware Revision Register [0xC004] [R]
- CPU Speed Register [0xC008] [R/W]
- Power Control Register [0xC00A] [R/W]
- Interrupt Enable Register [0xC00E] [R/W]
- Breakpoint Register [0xC014] [R/W]
- USB Diagnostic Register [0xC03C] [R/W]
- Memory Diagnostic Register [0xC03E] [W]
- External Memory Registers
- Timer Registers
- General USB Registers
- USB Host Only Registers
- Host n Control Register [R/W]
- Host n Address Register [R/W]
- Host n Count Register [R/W]
- Host n Endpoint Status Register [R]
- Host n PID Register [W]
- Host n Count Result Register [R]
- Host n Device Address Register [W]
- Host n Interrupt Enable Register [R/W]
- Host n Status Register [R/W]
- Host n SOF/EOP Count Register [R/W]
- Host n SOF/EOP Counter Register [R]
- Host n Frame Register [R]
- USB Device Only Registers
- Device n Endpoint n Control Register [R/W]
- Device n Endpoint n Address Register [R/W]
- Device n Endpoint n Count Register [R/W]
- Device n Endpoint n Status Register [R/W]
- Device n Endpoint n Count Result Register [R/W]
- Device n Port Select Register [R/W]
- Device n Interrupt Enable Register [R/W]
- Device n Address Register [W]
- Device n Status Register [R/W]
- Device n Frame Number Register [R]
- Device n SOF/EOP Count Register [W]
- OTG Control Registers
- GPIO Registers
- IDE Registers
- HSS Registers
- HSS Control Register [0xC070] [R/W]
- HSS Baud Rate Register [0xC072] [R/W]
- HSS Transmit Gap Register [0xC074] [R/W]
- HSS Data Register [0xC076] [R/W]
- HSS Receive Address Register [0xC078] [R/W]
- HSS Receive Counter Register [0xC07A] [R/W]
- HSS Transmit Address Register [0xC07C] [R/W]
- HSS Transmit Counter Register [0xC07E] [R/W]
- HPI Registers
- SPI Registers
- SPI Configuration Register [0xC0C8] [R/W]
- SPI Control Register [0xC0CA] [R/W]
- SPI Interrupt Enable Register [0xC0CC] [R/W]
- SPI Status Register [0xC0CE] [R]
- SPI Interrupt Clear Register [0xC0D0] [W]
- SPI CRC Control Register [0xC0D2] [R/W]
- SPI CRC Value Register [0xC0D4] [R/W]
- SPI Data Register [0xC0D6] [R/W]
- SPI Transmit Address Register [0xC0D8] [R/W]
- SPI Transmit Count Register [0xC0DA] [R/W]
- SPI Receive Address Register [0xC0DC [R/W]
- SPI Receive Count Register [0xC0DE] [R/W]
- UART Registers
- PWM Registers
- Processor Control Registers
- Pin Diagram
- Pin Descriptions
- Absolute Maximum Ratings
- Operating Conditions
- Crystal Requirements (XTALIN, XTALOUT)
- DC Characteristics
- AC Timing Characteristics
- Register Summary
- Ordering Information
- Package Diagrams
- Document History Page
- Sales, Solutions, and Legal Information
CY7C67300
Document #: 38-08015 Rev. *J Page 31 of 99
Register Description
The Host n Count register is used to hold the number of bytes
(packet length) for the current transaction. The maximum packet
length is 1023 bytes in ISO mode. The Host Count value is used
to determine how many bytes to transmit, or the maximum
number of bytes to receive. If the number of received bytes is
greater then the Host Count value then an overflow condition is
flagged by the Overflow bit in the Host n Endpoint Status register.
Port Select (Bit 14)
The Port Select bit selects which of the two active ports is
selected and is summarized in Tabl e 51.
1: Port 1B or Port 2B is enabled
0: Port 1A or Port 2A is enabled
Count (Bits [9:0])
The Count field sets the value for the current transaction data
packet length. This value is retained when switching between
host and device mode, and back again.
Reserved
Write all reserved bits with ’0’.
Host n Endpoint Status Register [R]
■ Host 1 Endpoint Status Register 0xC086
■ Host 2 Endpoint Status Register 0xC0A6
Register Description
The Host n Endpoint Status register is a read only register that
provides status for the last USB transaction.
Overflow Flag (Bit 11)
The Overflow Flag bit indicates that the received data in the last
data transaction exceeded the maximum length specified in the
Host n Count register. The Overflow Flag must be checked in
response to a Length Exception signified by the Length
Exception Flag set to ‘1’.
1: Overflow condition occurred
0: Overflow condition did not occur
Underflow Flag (Bit 10)
The Underflow Flag bit indicates that the received data in the last
data transaction was less than the maximum length specified in
the Host n Count register. The Underflow Flag must be checked
in response to a Length Exception signified by the Length
Exception Flag set to ‘1’.
1: Underflow condition occurred
0: Underflow condition did not occur
Stall Flag (Bit 7)
The Stall Flag bit indicates that the peripheral device replied with
a Stall in the last transaction.
1: Device returned Stall
0: Device did not return Stall
NAK Flag (Bit 6)
The NAK Flag bit indicates that the peripheral device replied with
a NAK in the last transaction.
1: Device returned NAK
0: Device did not return NAK
Length Exception Flag (Bit 5)
The Length Exception Flag bit indicates that the received data in
the data stage of the last transaction does not equal the
maximum Host Count specified in the Host n Count register. A
Length Exception can either mean an overflow or underflow and
the Overflow and Underflow flags (bits 11 and 10, respectively)
must be checked to determine which event occurred.
1: An overflow or underflow condition occurred
0: An overflow or underflow condition did not occur
Table 51. Port Select Definition
Port Select
Host/Device 1
Active Port
Host/Device 2
Active Port
0A A
1B B
Table 52. Host n Endpoint Status Register
Bit # 15 14 13 12 11 10 9 8
Field
Reserved Overflow
Flag
Underflow
Flag
Reserved
Read/Write - - - - R R - -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field
Stall
Flag
NAK
Flag
Length
Exception
Flag
Reserved Sequence
Status
Timeout
Flag
Error
Flag
ACK
Flag
Read/Write R R R - R R R R
Default 0 0 0 0 0 0 0 0
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