Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade Support Specification Sheet
Table Of Contents
- EZ-Host Features
- Typical Applications
- Introduction
- Functional Overview
- Interface Descriptions
- USB Interface
- OTG Interface
- External Memory Interface
- General Purpose IO Interface (GPIO)
- UART Interface
- I2C EEPROM Interface
- Serial Peripheral Interface
- High-Speed Serial Interface
- Programmable Pulse/PWM Interface
- Host Port Interface
- IDE Interface
- Charge Pump Interface
- Booster Interface
- Crystal Interface
- Boot Configuration Interface
- Operational Modes
- Power Savings and Reset Description
- Memory Map
- Registers
- Processor Control Registers
- CPU Flags Register [0xC000] [R]
- Bank Register [0xC002] [R/W]
- Hardware Revision Register [0xC004] [R]
- CPU Speed Register [0xC008] [R/W]
- Power Control Register [0xC00A] [R/W]
- Interrupt Enable Register [0xC00E] [R/W]
- Breakpoint Register [0xC014] [R/W]
- USB Diagnostic Register [0xC03C] [R/W]
- Memory Diagnostic Register [0xC03E] [W]
- External Memory Registers
- Timer Registers
- General USB Registers
- USB Host Only Registers
- Host n Control Register [R/W]
- Host n Address Register [R/W]
- Host n Count Register [R/W]
- Host n Endpoint Status Register [R]
- Host n PID Register [W]
- Host n Count Result Register [R]
- Host n Device Address Register [W]
- Host n Interrupt Enable Register [R/W]
- Host n Status Register [R/W]
- Host n SOF/EOP Count Register [R/W]
- Host n SOF/EOP Counter Register [R]
- Host n Frame Register [R]
- USB Device Only Registers
- Device n Endpoint n Control Register [R/W]
- Device n Endpoint n Address Register [R/W]
- Device n Endpoint n Count Register [R/W]
- Device n Endpoint n Status Register [R/W]
- Device n Endpoint n Count Result Register [R/W]
- Device n Port Select Register [R/W]
- Device n Interrupt Enable Register [R/W]
- Device n Address Register [W]
- Device n Status Register [R/W]
- Device n Frame Number Register [R]
- Device n SOF/EOP Count Register [W]
- OTG Control Registers
- GPIO Registers
- IDE Registers
- HSS Registers
- HSS Control Register [0xC070] [R/W]
- HSS Baud Rate Register [0xC072] [R/W]
- HSS Transmit Gap Register [0xC074] [R/W]
- HSS Data Register [0xC076] [R/W]
- HSS Receive Address Register [0xC078] [R/W]
- HSS Receive Counter Register [0xC07A] [R/W]
- HSS Transmit Address Register [0xC07C] [R/W]
- HSS Transmit Counter Register [0xC07E] [R/W]
- HPI Registers
- SPI Registers
- SPI Configuration Register [0xC0C8] [R/W]
- SPI Control Register [0xC0CA] [R/W]
- SPI Interrupt Enable Register [0xC0CC] [R/W]
- SPI Status Register [0xC0CE] [R]
- SPI Interrupt Clear Register [0xC0D0] [W]
- SPI CRC Control Register [0xC0D2] [R/W]
- SPI CRC Value Register [0xC0D4] [R/W]
- SPI Data Register [0xC0D6] [R/W]
- SPI Transmit Address Register [0xC0D8] [R/W]
- SPI Transmit Count Register [0xC0DA] [R/W]
- SPI Receive Address Register [0xC0DC [R/W]
- SPI Receive Count Register [0xC0DE] [R/W]
- UART Registers
- PWM Registers
- Processor Control Registers
- Pin Diagram
- Pin Descriptions
- Absolute Maximum Ratings
- Operating Conditions
- Crystal Requirements (XTALIN, XTALOUT)
- DC Characteristics
- AC Timing Characteristics
- Register Summary
- Ordering Information
- Package Diagrams
- Document History Page
- Sales, Solutions, and Legal Information
CY7C67300
Document #: 38-08015 Rev. *J Page 29 of 99
Port A SOF/EOP Enable (Bit 0)
The Port A SOF/EOP Enable bit is only applicable in host mode.
In device mode this bit must be written as ‘0’. In host mode this
bit enables or disables SOFs or EOPs for Port A. Either SOFs or
EOPs are generated depending on the LOA bit in the USB n
Control register when Port A is active.
1: Enable SOFs or EOPs
0: Disable SOFs or EOPs
Reserved
Write all reserved bits with ’0’.
USB Host Only Registers
There are twelve sets of dedicated registers for USB host only operation. Each set consists of two identical registers (unless otherwise
noted), one for Host Port 1 and one for Host Port 2. These register sets are covered in this section and summarized in Table 47.
Host n Control Register [R/W]
■ Host 1 Control Register 0xC080
■ Host 2 Control Register 0xC0A0
Register Description
The Host n Control register allows high level USB transaction
control.
Preamble Enable (Bit 7)
The Preamble Enable bit enables or disables the transmission of
a preamble packet before all low-speed packets. Set this bit only
when communicating with a low-speed device.
1: Enable Preamble packet
0: Disable Preamble packet
Table 47. USB Host Only Register
Register Name Address (Host 1/Host 2) R/W
Host n Control Register 0xC080/0xC0A0 R/W
Host n Address Register 0xC082/0xC0A2 R/W
Host n Count Register 0xC084/0xC0A4 R/W
Host n Endpoint Status Register 0xC086/0xC0A6 R
Host n PID Register 0xC086/0xC0A6 W
Host n Count Result Register 0xC088/0xC0A8 R
Host n Device Address Register 0xC088/0xC0A8 W
Host n Interrupt Enable Register 0xC08C/0xC0AC R/W
Host n Status Register 0xC090/0xC0B0 R/W
Host n SOF/EOP Count Register 0xC092/0xC0B2 R/W
Host n SOF/EOP Counter Register 0xC094/0xC0B4 R
Host n Frame Register 0xC096/0xC0B6 R
Table 48. Host n Control Register
Bit # 15 14 13 12 11 10 9 8
Field Reserved
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field
Preamble
Enable
Sequence
Select
Sync
Enable
ISO
Enable
Reserved Arm
Enable
Read/Write R/W R/W R/W R/W - - - R/W
Default 0 0 0 0 0 0 0 0
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