Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade Support Specification Sheet
Table Of Contents
- EZ-Host Features
- Typical Applications
- Introduction
- Functional Overview
- Interface Descriptions
- USB Interface
- OTG Interface
- External Memory Interface
- General Purpose IO Interface (GPIO)
- UART Interface
- I2C EEPROM Interface
- Serial Peripheral Interface
- High-Speed Serial Interface
- Programmable Pulse/PWM Interface
- Host Port Interface
- IDE Interface
- Charge Pump Interface
- Booster Interface
- Crystal Interface
- Boot Configuration Interface
- Operational Modes
- Power Savings and Reset Description
- Memory Map
- Registers
- Processor Control Registers
- CPU Flags Register [0xC000] [R]
- Bank Register [0xC002] [R/W]
- Hardware Revision Register [0xC004] [R]
- CPU Speed Register [0xC008] [R/W]
- Power Control Register [0xC00A] [R/W]
- Interrupt Enable Register [0xC00E] [R/W]
- Breakpoint Register [0xC014] [R/W]
- USB Diagnostic Register [0xC03C] [R/W]
- Memory Diagnostic Register [0xC03E] [W]
- External Memory Registers
- Timer Registers
- General USB Registers
- USB Host Only Registers
- Host n Control Register [R/W]
- Host n Address Register [R/W]
- Host n Count Register [R/W]
- Host n Endpoint Status Register [R]
- Host n PID Register [W]
- Host n Count Result Register [R]
- Host n Device Address Register [W]
- Host n Interrupt Enable Register [R/W]
- Host n Status Register [R/W]
- Host n SOF/EOP Count Register [R/W]
- Host n SOF/EOP Counter Register [R]
- Host n Frame Register [R]
- USB Device Only Registers
- Device n Endpoint n Control Register [R/W]
- Device n Endpoint n Address Register [R/W]
- Device n Endpoint n Count Register [R/W]
- Device n Endpoint n Status Register [R/W]
- Device n Endpoint n Count Result Register [R/W]
- Device n Port Select Register [R/W]
- Device n Interrupt Enable Register [R/W]
- Device n Address Register [W]
- Device n Status Register [R/W]
- Device n Frame Number Register [R]
- Device n SOF/EOP Count Register [W]
- OTG Control Registers
- GPIO Registers
- IDE Registers
- HSS Registers
- HSS Control Register [0xC070] [R/W]
- HSS Baud Rate Register [0xC072] [R/W]
- HSS Transmit Gap Register [0xC074] [R/W]
- HSS Data Register [0xC076] [R/W]
- HSS Receive Address Register [0xC078] [R/W]
- HSS Receive Counter Register [0xC07A] [R/W]
- HSS Transmit Address Register [0xC07C] [R/W]
- HSS Transmit Counter Register [0xC07E] [R/W]
- HPI Registers
- SPI Registers
- SPI Configuration Register [0xC0C8] [R/W]
- SPI Control Register [0xC0CA] [R/W]
- SPI Interrupt Enable Register [0xC0CC] [R/W]
- SPI Status Register [0xC0CE] [R]
- SPI Interrupt Clear Register [0xC0D0] [W]
- SPI CRC Control Register [0xC0D2] [R/W]
- SPI CRC Value Register [0xC0D4] [R/W]
- SPI Data Register [0xC0D6] [R/W]
- SPI Transmit Address Register [0xC0D8] [R/W]
- SPI Transmit Count Register [0xC0DA] [R/W]
- SPI Receive Address Register [0xC0DC [R/W]
- SPI Receive Count Register [0xC0DE] [R/W]
- UART Registers
- PWM Registers
- Processor Control Registers
- Pin Diagram
- Pin Descriptions
- Absolute Maximum Ratings
- Operating Conditions
- Crystal Requirements (XTALIN, XTALOUT)
- DC Characteristics
- AC Timing Characteristics
- Register Summary
- Ordering Information
- Package Diagrams
- Document History Page
- Sales, Solutions, and Legal Information
CY7C67300
Document #: 38-08015 Rev. *J Page 16 of 99
Registers
Some registers have different functions for a read vs. a write
access or USB host vs. USB device mode. Therefore, registers
of this type have multiple definitions for the same address.
The default register values listed in this data sheet may be
altered to some other value during the BIOS initialization. Refer
to the BIOS documentation for register initialization information.
Processor Control Registers
There are nine registers dedicated to general processor control.
Each of these registers are covered in this section and are
summarized in Table 21.
CPU Flags Register [0xC000] [R]
Register Description
The CPU Flags register is a read only register that gives
processor flags status.
Global Interrupt Enable (Bit 4)
The Global Interrupt Enable bit indicates if the Global Interrupts
are enabled.
1: Enabled
0: Disabled
Negative Flag (Bit 3)
The Negative Flag bit indicates if an arithmetic operation results
in a negative answer.
1: MS result bit is ‘1’
0: MS result bit is not ‘1’
Overflow Flag (Bit 2)
The Overflow Flag bit indicates if an overflow condition occurred.
An overflow condition can occur if an arithmetic result was either
larger than the destination operand size (for addition) or smaller
than the destination operand must allow for subtraction.
1: Overflow occurred
0: Overflow did not occur
Carry Flag (Bit 1)
The Carry Flag bit indicates if an arithmetic operation resulted in
a Carry for addition, or Borrow for subtraction.
1: Carry/Borrow occurred
0: Carry/Borrow did not occur
Zero Flag (Bit 0)
The Zero Flag bit indicates if an instruction execution resulted in
a ‘0’.
1: Zero occurred
0: Zero did not occur
Table 21. Processor Control Registers
Register Name Address R/W
CPU Flags Register 0xC000 R
Register Bank Register 0xC002 R/W
Hardware Revision Register 0xC004 R
CPU Speed Register 0xC008 R/W
Power Control Register 0xC00A R/W
Interrupt Enable Register 0xC00E R/W
Breakpoint Register 0xC014 R/W
USB Diagnostic Register 0xC03C W
Memory Diagnostic Register 0xC03E W
Table 22. CPU Flags Register
Bit # 15 14 13 12 11 10 9 8
Field Reserved...
Read/Write - - - - - - - -
Default 0 0 0 0 0 0 0 0
Bit # 7 6 5 4 3 2 1 0
Field
...Reserved Global
Interrupt
Enable
Negative
Flag
Overflow
Flag
Carry
Flag
Zero
Flag
Read/Write - - - R R R R R
Default 0 0 0 X X X X X
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