Data Sheet
Table Of Contents
- CYSBSYS-RP01, Rapid IoT Connect
- General Description
- Key Features
- Package
- Benefits
- Ordering Information
- Contents
- Overview
- Functional Block Diagram
- PSoC 6 MCU
- Dual-band 802.11ac-friendly Radio with BT 5.0
- Crystal and Oscillators
- Chip Antenna for Wi-Fi / BT and u.FL Connector
- CapSense® External Modulation and Integration Capacitors
- Mechanical Dimensions
- Castellated Pads Layout
- Recommended Host PCB Layout
- System Connections
- Castellated Pads Pin Description
- External Reset (XRES)
- Electrical Specifications
- Recommended Operating Conditions
- External ECO Specification
- Environmental Conditions
- ESD and EMI Protection
- Regulatory Information
- Packaging
- Ordering Information
- Part Numbering Convention
- Acronyms
- Document Conventions
- Sales, Solutions, and Legal Information
PRELIMINARY
CYSBSYS-RP01
System Connections
Power Supply Connections and Recommended External Components
Figure 6 shows the general requirements for power pins on CYSBSYS-RP01. See the DC Specifications table for details on the entire
range of supported voltage for each power pins.
Figure 6. Board Power Pad Connections
1.8V
C23
10uF
10V
1.8V~3.3V
50
U1A
VDDD
VBAT_WL1
VBAT_WL2
22
23
3.6V~4.2V
GND
1.8V *
C38
10uF
10V
1.8V
65
VDDA
VDDIO_WL
25
C1
4.7uF
25V
GND
1.8V
VBACKUP
C2
4.7uF
GND
C40
1uF
25V
1.8V~3.3V
C39
1uF
25V
55
67
VDDIO0
VDDIO1
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
1
2
3
4
5
6
14
24
GND
25V
Notes:
VDDIO1 should be ≥ to VDDA.
VDDUSB should be minimum
2.85 V for USB
1.8V~3.3V
GND
54
GND10
GND11
VDDUSB GND12
51
59
73
C3
1uF
25V
CYSBSYS-RP01
GND
GND
Bypass capacitors must be used from VBAT_WL, VDDD, and VDDA to ground and wherever indicated in the diagram. Typical practice
for systems in this frequency range is to use a capacitor in the 10-µF range. A parallel smaller capacitor for each domain is provided
on the CYSBSYS-RP01 board. Note that these are rules of thumb: for critical applications, the PCB layout, lead inductance, and the
bypass capacitor parasitic should be simulated to design and obtain optimal bypassing. All capacitors should be ±20%, X5R ceramic
or better.
Power supplies and ports correspond as follows:
■ P0: VBACKUP
■ P5, P6, P7, P8: VDDIO1
■ P9, P10: VDDIO, VDDA
■ P11, P12, P13: VDDIO0
Document Number: 002-29368 Rev. *C
Page 8 of 22
GND
56
GND9
37