Datasheet

CY8C24123A
CY8C24223A
CY8C24423A
Document Number: 38-12028 Rev. *R Page 34 of 65
AC Electrical Characteristics
AC Chip-Level Specifications
These tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C  T
A
 85 °C, 3.0 V to 3.6 V and –40 °C  T
A
 85 °C, or 2.4 V to 3.0 V and –40 °C  T
A
 85 °C, respectively. Typical parameters
are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only.
Table 29. 5-V and 3.3-V AC Chip-Level Specifications
Symbol Description Min Typ Max Units Notes
F
IMO24
Internal main oscillator (IMO) frequency for
24 MHz
23.4 24 24.6
[18,19]
MHz Trimmed for 5 V or 3.3 V operation
using factory trim values.
See Figure 8 on page 16.
SLIMO mode = 0.
F
IMO6
IMO frequency for 6 MHz 5.5 6 6.5
[18,19]
MHz Trimmed for 5 V or 3.3 V operation
using factory trim values.
See Figure 8 on page 16.
SLIMO mode = 1.
F
CPU1
CPU frequency (5 V nominal) 0.937 24 24.6
[18]
MHz SLIMO mode = 0.
F
CPU2
CPU frequency (3.3 V nominal) 0.937 12 12.3
[19]
MHz SLIMO mode = 0.
F
48M
Digital PSoC block frequency 0 48 49.2
[18,20]
MHz Refer to the AC Digital Block
Specifications.
F
24M
Digital PSoC block frequency 0 24 24.6
[20]
MHz
F
32K1
ILO frequency 15 32 64 kHz
F
32K2
External crystal oscillator – 32.768 – kHz Accuracy is capacitor and crystal
dependent. 50% duty cycle.
F
32K_U
ILO untrimmed frequency 5 – 100 kHz After a reset and before the M8C
starts to run, the ILO is not trimmed.
See the System Resets section of
the PSoC Technical Reference
Manual for details on timing this
F
PLL
PLL frequency – 23.986 – MHz Is a multiple (x732) of crystal
frequency.
T
PLLSLEW
PLL lock time 0.5 – 10 ms
T
PLLSLEWSLOW
PLL lock time for low gain setting 0.5 – 50 ms
T
OS
External crystal oscillator startup to 1% – 1700 2620 ms
T
OSACC
External crystal oscillator startup to
100 ppm
– 2800 3800 ms The crystal oscillator frequency is
within 100 ppm of its final value by
the end of the T
osacc
period. Correct
operation assumes a properly
loaded 1 µW maximum drive level
32.768 kHz crystal.
3.0 V  V
DD
 5.5 V,
–40 °C  T
A
 85 °C.
t
XRST
External reset pulse width 10 – – s
DC24M 24 MHz duty cycle 40 50 60 %
DC
ILO
ILO duty cycle 20 50 80 %
Step24M 24 MHz trim step size – 50 – kHz
Fout48M 48 MHz output frequency 46.8 48.0 49.2
[18,19]
MHz Trimmed. Using factory trim values.
F
MAX
Maximum frequency of signal on row input
or row output.
– – 12.3 MHz
SR
POWER_UP
Power supply slew rate – – 250 V/ms V
DD
slew rate during power-up.
t
POWERUP
Time from end of POR to CPU executing
code
– 16 100 ms Power-up from 0 V. See the System
Resets section of the PSoC
Technical Reference Manual.
Notes
18. 4.75 V < V
DD
< 5.25 V.
19. 3.0 V < V
DD
< 3.6 V. See application note Adjusting PSoC
®
Trims for 3.3 V and 2.7 V Operation – AN2012 for information on trimming for operation at 3.3 V.
20. See the individual user module datasheets for information on maximum frequencies for user modules.
21. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.