QDRTM-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) Specification Sheet

CY7C1541V18, CY7C1556V18
CY7C1543V18, CY7C1545V18
Document Number: 001-05389 Rev. *F Page 21 of 28
I
SB1
Automatic Power down
Current
Max V
DD
,
Both Ports Deselected,
V
IN
≥ V
IH
or V
IN
≤ V
IL
f = f
MAX
= 1/t
CYC
, Inputs
Static
375 MHz x8 525 mA
x9 525
x18 525
x36 410
333 MHz x8 500 mA
x9 500
x18 500
x36
395
300 MHz x8 450 mA
x9 450
x18
450
x36 385
AC Electrical Characteristics
Over the Operating Range
[14]
Parameter Description Test Conditions Min Typ Max Unit
V
IH
Input HIGH Voltage V
REF
+ 0.2 – V
DDQ
+ 0.24 V
V
IL
Input LOW Voltage –0.24 – V
REF
– 0.2 V
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter Description Test Conditions Max Unit
C
IN
Input Capacitance T
A
= 25°C, f = 1 MHz, V
DD
= 1.8V, V
DDQ
= 1.5V 5 pF
C
CLK
Clock Input Capacitance 6 pF
C
O
Output Capacitance 7pF
Electrical Characteristics (continued)
DC Electrical Characteristics
Over the Operating Range
[15]
Parameter Description Test Conditions Min Typ Max Unit
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