QDRTM-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) Specification Sheet

CY7C1541V18, CY7C1556V18
CY7C1543V18, CY7C1545V18
Document Number: 001-05389 Rev. *F Page 15 of 28
TAP Controller Block Diagram
TAP Electrical Characteristics
Over the Operating Range
[13, 14, 15]
Parameter Description Test Conditions Min Max Unit
V
OH1
Output HIGH Voltage I
OH
= −2.0 mA 1.4 V
V
OH2
Output HIGH Voltage I
OH
= −100 μA1.6 V
V
OL1
Output LOW Voltage I
OL
= 2.0 mA 0.4 V
V
OL2
Output LOW Voltage I
OL
= 100 μA0.2V
V
IH
Input HIGH Voltage 0.65V
DD
V
DD
+ 0.3 V
V
IL
Input LOW Voltage –0.3 0.35V
DD
V
I
X
Input and Output Load Current GND ≤ V
I
≤ V
DD
–5 5 μA
0
012..293031
Boundary Scan Register
Identification Register
012....108
012
Instruction Register
Bypass Register
Selection
Circuitry
Selection
Circuitry
TAP Controller
TDI
TDO
TCK
TMS
Notes
13. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
14. Overshoot: V
IH
(AC) < V
DDQ
+ 0.35V (Pulse width less than t
CYC
/2), Undershoot: V
IL
(AC) > −0.3V (Pulse width less than t
CYC
/2).
15. All Voltage referenced to Ground.
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