Dual-Port Static RAM with SEM, INT, BUSY Specification Sheet

CY7C145, CY7C144
Document #: 38-06034 Rev. *D Page 3 of 21
Figure 3. 80-Pin TQFP
Pin Configurations (continued)
Table 1. Pin Definitions
Left Port Right Port Description
I/O
0L7L(8L)
I/O
0R7R(8R)
Data bus Input/Output
A
0L12L
A
0R12R
Address Lines
CE
L
CE
R
Chip Enable
OE
L
OE
R
Output Enable
R/W
L
R/W
R
Read/Write Enable
SEM
L
SEM
R
Semaphore Enable. When asserted LOW, allows access to eight semaphores. The three least signif-
icant bits of the address lines will determine which semaphore to write or read. The I/O
0
pin is used
when writing to a semaphore. Semaphores are requested by writing a 0 into the respective location.
INT
L
INT
R
Interrupt Flag. INT
L
is set when right port writes location 1FFE and is cleared when left port reads
location 1FFE. INT
R
is set when left port writes location 1FFF and is cleared when right port reads
location 1FFF.
BUSY
L
BUSY
R
Busy Flag
M/S
Master or Slave Select
V
CC
Power
GND Ground
Table 2. Selection Guide
Description
7C144-15
7C145-15
7C144-25
7C145-25
7C144-35
7C145-35
7C144-55
7C145-55
Unit
Maximum Access Time 15 25 35 55 ns
Maximum Operating Current 220 180 160 160 mA
Maximum Standby Current for I
SB1
60 40 30 30 mA
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