Dual-Port Static RAM Specification Sheet
CY7C130, CY7C130A
CY7C131, CY7C131A
CY7C140, CY7C141
Document #: 38-06002 Rev. *E Page 6 of 19
Switching Characteristics
Over the Operating Range
[7, 12]
Parameter Description
7C131-15
[4]
7C131A-15
7C141-15
7C130-25
[4]
7C131-25
7C140-25
7C141-25
7C130-30
7C130A-30
7C131-30
7C140-30
7C141-30
Unit
Min Max Min Max Min Max
Read Cycle
t
RC
Read Cycle Time 15 25 30 ns
t
AA
Address to Data Valid
[13]
15 25 30 ns
t
OHA
Data Hold from Address Change 0 00ns
t
ACE
CE LOW to Data Valid
[13]
15 25 30 ns
t
DOE
OE LOW to Data Valid
[13]
10 15 20 ns
t
LZOE
OE LOW to Low Z
[10, 14, 15]
3 33ns
t
HZOE
OE HIGH to High Z
[10, 14, 15]
10 15 15 ns
t
LZCE
CE LOW to Low Z
[10, 14, 15]
3 55ns
t
HZCE
CE HIGH to High Z
[10, 14, 15]
10 15 15 ns
t
PU
CE LOW to Power Up
[10]
0 00ns
t
PD
CE HIGH to Power Down
[10]
15 25 25 ns
Write Cycle
[16]
t
WC
Write Cycle Time 15 25 30 ns
t
SCE
CE LOW to Write End 12 20 25 ns
t
AW
Address Setup to Write End 12 20 25 ns
t
HA
Address Hold from Write End 2 22ns
t
SA
Address Setup to Write Start 0 00ns
t
PWE
R/W Pulse Width 12 15 25 ns
t
SD
Data Setup to Write End 10 15 15 ns
t
HD
Data Hold from Write End 0 00ns
t
HZWE
R/W LOW to High Z
[15]
10 15 15 ns
t
LZWE
R/W HIGH to Low Z
[15]
0 00ns
Shaded areas contain preliminary information.
Notes
12. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified
I
OL
/I
OH,
and 30 pF load capacitance.
13. AC Test Conditions use V
OH
= 1.6V and V
OL
= 1.4V.
14. At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
15. t
LZCE
, t
LZWE
, t
HZOE
, t
LZOE
, t
HZCE
and t
HZWE
are tested with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
16. The internal write time of the memory is defined by the overlap of CS
LOW and R/W LOW. Both signals must be low to initiate a write and either signal can
terminate a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
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