Synchronous Dual-Port Static RAM Specification Sheet

CY7C09079V/89V/99V
CY7C09179V/89V/99V
Document #: 38-06043 Rev. *C Page 8 of 21
Switching Waveforms (continued)
Figure 6. Read Cycle for Flow-Through Output (FT
/PIPE = V
IL
)
[16, 17, 18, 19]
Notes
16. OE
is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
17. ADS
= V
IL
, CNTEN and CNTRST = V
IH
.
18. The output is disabled (high-impedance state) by CE
0
=V
IH
or CE
1
= V
IL
following the next rising edge of the clock.
19. Addresses do not have to be accessed sequentially since ADS
= V
IL
constantly loads the address on the rising edge of the CLK. Numbers are for reference
only.
t
CH1
t
CL1
t
CYC1
t
SC
t
HC
t
DC
t
OHZ
t
OE
t
SC
t
HC
t
SW
t
HW
t
SA
t
HA
t
CD1
t
CKHZ
t
DC
t
OLZ
t
CKLZ
A
n
A
n+1
A
n+2
A
n+3
Q
n
Q
n+1
Q
n+2
CLK
CE
0
CE
1
R/W
ADDRESS
DATA
OUT
OE
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