Synchronous Dual-Port Static RAM Specification Sheet

CY7C09079V/89V/99V
CY7C09179V/89V/99V
Document #: 38-06043 Rev. *C Page 14 of 21
Figure 14. Pipelined Read with Address Counter Advance
[29]
Figure 15. Flow-Through Read with Address Counter Advance
[29]
Note
29. CE
0
and OE = V
IL
; CE
1
, R/W and CNTRST = V
IH
.
Switching Waveforms (continued)
COUNTER HOLD
READ WITH COUNTER
t
SA
t
HA
t
SAD
t
HAD
t
SCN
t
HCN
t
CH2
t
CL2
t
CYC2
t
SAD
t
HAD
t
SCN
t
HCN
Q
x-1
Q
x
Q
n
Q
n+1
Q
n+2
Q
n+3
t
DC
t
CD2
READ WITH COUNTER
READ
EXTERNAL
ADDRESS
CLK
ADDRESS
ADS
DATA
OUT
CNTEN
A
n
t
CH1
t
CL1
t
CYC1
t
SA
t
HA
t
SAD
t
HAD
t
SCN
t
HCN
A
n
t
SAD
t
HAD
t
SCN
t
HCN
CLK
ADDRESS
ADS
CNTEN
Q
x
Q
n
Q
n+1
t
DC
COUNTER HOLD
READ WITH COUNTER
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
Q
n+3
Q
n+2
DATA
OUT
t
CD1
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