Stellaris® LM3S9B96 Development Kit User ’s Manual DK-LM3S9B96 -05 Co pyrigh t © 2 009– 201 0 Te xas In strumen ts
Copyright Copyright © 2009–2010 Texas Instruments, Inc. All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments. ARM and Thumb are registered trademarks, and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. Texas Instruments 108 Wild Basin, Suite 350 Austin, TX 78746 http://www.ti.
Stellaris® LM3S9B96 Development Kit User’s Manual Table of Contents Chapter 1: Stellaris® LM3S9B96 Development Board Overview ................................................................. 7 Features.............................................................................................................................................................. 7 Development Kit Contents ...........................................................................................................................
SRAM............................................................................................................................................................ 52 Configuration PROM..................................................................................................................................... 52 Configuration Pushbutton ............................................................................................................................. 52 Test Port .............................
Stellaris® LM3S9B96 Development Kit User’s Manual List of Figures Figure 1-1. Figure 1-2. Figure 2-1. Figure 4-1. Figure B-1. Figure E-1. Figure E-2. Figure E-3. Figure E-4. Figure F-1. Figure F-2. Figure F-3. Figure F-4. Figure F-5. Figure F-6. Figure G-1. Figure G-2. Figure G-3. Figure G-4. Figure G-5. Figure G-6. Figure G-7. Figure G-8. DK-LM3S9B96 Development Board................................................................................................
List of Tables Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. Table C-1. Table D-1. Table E-1. Table E-2. Table F-1. Table F-2. Table F-3. Table F-4. Table F-5. Table F-6. Table F-7. Table F-8. Table G-1. 6 Board Features and Peripherals that are Disconnected in Factory Default Configuration ............ 13 USB-Related Signals.....................................................................................................................
C H A P T E R 1 Stellaris® LM3S9B96 Development Board Overview The Stellaris® LM3S9B96 Development Board provides a platform for developing systems around the advanced capabilities of the LM3S9B96 ARM® Cortex™-M3-based microcontroller. The LM3S9B96 is a member of the Stellaris Tempest-class microcontroller family. Tempest-class devices include capabilities such as 80 MHz clock speeds, an External Peripheral Interface (EPI) and Audio I2S interfaces.
User LED and push button Thumbwheel potentiometer (can be used for menu navigation) MicroSD card slot Supports a range of debugging options – Integrated In-circuit Debug Interface (ICDI) – JTAG, SWD, and SWO all supported – Standard ARM® 20-pin JTAG debug connector USB Virtual COM Port Jumper shunts to conveniently reallocate I/O resources Develop using tools supporting Keil™ RealView® Microcontroller Development Kit (MDK-ARM), IAR Embedded Workbench, Code Sourcery GCC development
Stellaris® LM3S9B96 Development Kit User’s Manual Figure 1-1.
Development Kit Contents The Stellaris® LM3S9B96 Development Kit contains everything needed to develop and run a range of applications using Stellaris microcontrollers: LM3S9B96 development board 8 MB SDRAM expansion board EPI signal breakout board Retractable Ethernet cable USB Mini-B cable for debugger use USB Micro-B cable for OTG-to-PC connection USB Micro-A to USB A adapter for USB Host USB Flash memory stick microSD Card 20-position ribbon cable CD containing
Stellaris® LM3S9B96 Development Kit User’s Manual Block Diagram DK-LM3S9B96 Development Board Block Diagram Target Cable Figure 1-2. I/O Signal Break-out SWD/JTAG Mux Debug USB USB Touch T Dual USB Device Controller Debug I/O Signal Break-out JTAG/SWD Output/Input QVGA Color LCD Module Debug UART0 OTG/Host/Device USB USB micro-AB connector +5V host supply +3.
Dimensions (excluding LCD panel): – 4.50” x 4.25” x 0.60” (LxWxH) with SDRAM board – 4.50” x 4.25” x 0.75” (LxWxH) with EPI breakout board Analog Reference: 3.0 V +/-0.2% RoHS status: Compliant NOTE: When the LM3S9B96 Development Board is used in USB Host mode, the host connector is capable of supplying power to the connected USB device. The available supply current is limited to ~200 mA unless the development board is powered from an external 5 V supply with a =600mA rating.
C H A P T E R 2 Stellaris® LM3S9B96 Development Board Hardware Description In addition to an LM3S9B96 microcontroller, the development board includes a range of useful peripheral features and an integrated in-circuit debug interface (ICDI).
assignments that are supported by the 0.1” jumpers and PCB routing. The LM3S9B96 has additional internal multiplexing that enables additional configurations which may require discrete wiring between peripherals and GPIO pins. The ICDI section of the board has a GND-GND jumper that serves no function other than to provide a convenient place to ‘park’ a spare jumper. This jumper may be reused as required. Figure 2-1. Factory Default Jumper Settings Clocking The development board uses a 16.
Stellaris® LM3S9B96 Development Kit User’s Manual Reset The RESETn signal into the LM3S9B96 microcontroller connects to the reset switch (SW2) and to the ICDI circuit for a debugger-controlled reset.
more than 1 Amp, or if the switches’ thermal limits are exceeded by a device drawing more than 500 mA. USB0PFLT indicates the over-current status back to the microcontroller. The development board can be either a bus-powered USB device or self-powered USB device depending on the power-supply configuration jumpers. When using the development board in USB-host mode, power to the EVB should be supplied by the In-circuit Debugger (ICDI) USB cable or by a +5 V source connected to the DC power jack.
Stellaris® LM3S9B96 Development Kit User’s Manual A small serial EEPROM holds the FT2232 configuration data. The EEPROM is not accessible by the LM3S9B96 microcontroller. For full details on FT2232 operation, go to www.ftdichip.com. USB to JTAG/SWD The FT2232 USB device performs JTAG/SWD serial operations under the control of the debugger. A simple logic circuit multiplexes SWD and JTAG functions and, when working in SWD mode, provides direction control for the bidirectional data line.
Wide temperature range White LED backlight Integrated RAM Resistive touch panel Control Interface The Color LCD module has a built-in controller IC with a multi-mode parallel interface. The development board uses an 8-bit 8080 type interface with GPIO Port D providing the data bus. Table 2-4 shows the LCD-related signals. Table 2-5.
Stellaris® LM3S9B96 Development Kit User’s Manual I2S Audio The LM3S9B96 development board has advanced audio capabilities using an I2S-connected Audio TLV320AIC23 CODEC. The factory default configuration has Audio output (Line Out and/or Headphone output) enabled. Four additional I2S signals are required for Audio input (Line Input and/or Microphone). All four audio interfaces are through 1/8” (3.5mm) stereo jacks. Table 2-6 shows the I2S audio-related signals. Table 2-6.
September 5, 2010
C H A P T E R 3 Stellaris® LM3S9B96 Development Board External Peripheral Interface (EPI) The External Peripheral Interface (EPI) is a high-speed 8/16/32-bit parallel bus for connecting external peripherals or memory without glue logic. Supported modes include SDRAM, SRAM, and Flash memories, as well as Host-bus and FIFO modes. The LM3S9B96 development kit includes an 8 MB SDRAM board in addition to an EPI break-out board. Other EPI expansion boards may be available.
September 5, 2010
C H A P T E R 4 Using the In-Circuit Debugger Interface The Stellaris® LM3S9B96 Development Kit can operate as an In-Circuit Debugger Interface (ICDI). ICDI acts as a USB to the JTAG/SWD adaptor, allowing debugging of any external target board that uses a Stellaris microcontroller. See “Debugging Modes” on page 16 for a description of how to enter ICDI Out mode. Figure 4-1.
September 5, 2010
A P P E N D I X A Stellaris® LM3S9B96 Development Board Schematics This section contains the schematics for the DK-LM3S9B96 development board.
Schematic page 1 4 PC0/TCK PC1/TMS PC2/TDI PC3/TDO 80 79 78 77 25 24 23 22 PC4/EPI02 PC5/EPI03 PC6/EPI04 PC7/EPI05 PE0/EPI08 PE1/EPI09 PE2/EPI24 PE3/EPI25 B 74 75 95 96 6 5 2 1 PE4/I2STXWS PE5/I2STXSD PE6/ADC1 PE7/ADC0 PG0/EPI13 PG1/EPI14 PG7/EPI31 19 18 36 PJ0/EPI16 PJ1/EPI17 PJ2/EPI18 PJ3/EPI19 PJ4/EPI28 PJ5/EPI29 PJ6/EPI30 14 87 39 50 52 53 54 55 PJ7 64 RESETn PA0/U0RX PA1/U0TX PA2/SSI0CLK PA3/SSI0FSS PA4/SSI0RX PA5/SSI0TX PA6/USB0EPEN PA7/USB0PFLT PB0/USB0ID PB1/USB0VBUS PB2/CCP0 PB3 PB4/
Schematic page 2 2 3 +3.3V GND DO DATA0 RSV DATA1 JP12 LED_A JP16 PE6/ADC1 JP17 PE3/EPI25 JP18 PE2/EPI24 +3.3V 12 11 9 10 RESETn 100 C26 0.1UF JP19 PE7/ADC0 R16 10K LED_K ILED+ R59 SW-B3S1000 CARD JP13 ILED- FR4 MISO PA4/SSI0RX SW2 N/C DATA2 CS DATA3 DI CMD VDD 2908-05WB-MG CLOCK FR3 JP11 MISO R19 10K Reset 1 2 3 4 5 6 7 8 +3.3V SSICLK PA2/SSI0CLK X+ TOUCH_XP TOUCH_YN TOUCH_XN TOUCH_YP YX- XR YD XL YU +3.3V Y+ C28 C30 C31 C33 0.01UF 0.01UF 0.01UF 0.
Schematic page 3 1 2 3 4 5 6 TP1 3.3V +3.3V P3V U5 PQ1LA333MSPQ TP3 5.0V DBG+5V +VBUS 4 +5V ICDI 3 C34 0.1UF VOUT A M+3.3V M3V 5 NR 1 C42 2.2UF C39 TP2 GND 0.01UF 2 1 3 2 PJ-002BH-SMT ON C37 2.2UF JP35 EXT J7 VIN JP61 JP34 OTG +5V DC INPUT JP60 +5V GND A GND JP59 JP36 Main +3.3V Supply Power Source Selection +3.3V B EPEN PA6/USBEPE/CAN0RX JP37 PFLT PA7/USBPFLT/CAN0TX U6 TPS2051BDBV +VBUS +5V 5 USB0EPE 4 3 IN EN OCn USB0PFLT B 1 C40 2.
Schematic page 4 1 2 J8 3 4.7K R55 STX-3000 0.47UF R56 4.7K R30 10K 1 2 3 Microphone Input C47 R28 10K STX-3000 6 C79 0.47UF 4.7K A J9 5 C77 R54 1 2 3 Line Input 4 C76 27PF C48 2.2UF R57 4.7K A C78 27PF R31 4.7K 27PF C54 R27 4.7K B + +3.3V R29 4.7K SDA 20 19 17 18 PB3/I2C0SDA JP40 SCL MICBIAS MICIN PB2/I2C0SCL JP41 TXSD PE5/I2STXSD TXSD 23 24 22 21 Rework 2: Loop TXWS to RXWS.
Schematic page 5 1 2 3 4 5 6 SDRAM Expansion Board U10 A Expansion Connector J12 AD2 AD3 AD4 AD5 +3.3V C62 2.
Schematic page 6 2 3 4 5 6 13 1 TCK 11 1 12 Debugger USB Interface 2 54819-0572 D- D+ ID G R43 U13A SN74LVC125A +3.3V 7 USBSH 7 USBDM USBDP R44 1.5K B +5V R39 10K U11 VCC NC ORG GND CS SK DI DO 1 2 3 4 48 1 2 47 R40 1.5K CAT93C46 43 44 1K 64X16 1 Y3 2 4 5 +5V 6.
September 5, 2010
A P P E N D I X B Stellaris® LM3S9B96 Development Board Component Locations This appendix contains details on component locations, including: Component placement plot for top (Figure B-1) September 5, 2010 33
Figure B-1.
A P P E N D I X C Stellaris® LM3S9B96 Development Board Connection Details This appendix contains the following sections: DC Power Jack (see page 35) ARM Target Pinout (see page 35) DC Power Jack The EVB provides a DC power jack for connecting an external +5 V regulated (+/-5%) power source. Center Positive (+) The socket is 5.5 mm dia with a 2.1 mm pin. ARM Target Pinout In ICDI input and output mode, the Stellaris® LM3S9B96 Development Kit supports ARM’s standard 20-pin JTAG/SWD configuration.
September 5, 2010
A P P E N D I X D Stellaris® LM3S9B96 Development Board Microcontroller GPIO Assignments Table D-1 shows the pin assignments for the LM3S9B96 microcontroller. Table D-1.
Table D-1. Microcontroller GPIO Assignments (Continued) LM3S9B96 GPIO Pin Number 38 Development Board Use Description Default Function 10 PD0 PD0 11 PD1 12 Default Use Alt.
Stellaris® LM3S9B96 Development Kit User’s Manual Table D-1. Microcontroller GPIO Assignments (Continued) LM3S9B96 GPIO Pin Number Development Board Use Description Default Function Alt.
September 5, 2010
A P P E N D I X E Stellaris® LM3S9B96 Flash and SRAM Memory Expansion Board This document describes the Flash and SRAM memory expansion board (DK-LM3S9B96-EXP-FS8) plug-in for the DK-LM3S9B96 development board. This expansion board works with the External Peripheral Interface (EPI) port of the Stellaris microcontroller and provides Flash memory, SRAM, and an improved performance LCD interface. Figure E-1.
3. On the DK-LM3S9B96 board remove the shunt jumpers on JP16-JP31 and the JP39 headers as shown in Figure E-1 on page 41. Figure E-2. Removing EPI Board from DK-LM3S9B96 Development Board Remove board Remove jumpers 4. Install the two snap-in nylon standoffs on mounting holes above the EPI connector J2. 5. Place the expansion board on top of the DK-LM3S9B96 board and align the standoffs, the EPI connector, and the 2x17 J2 header. 6.
Stellaris® LM3S9B96 Development Kit User’s Manual Hardware Description The Flash and SRAM memory expansion board is designed for use with the Stellaris EPI module configured in Host Bus 8 address/data multiplexed mode. This mode requires the use of an external 8-bit latch for storing the lower 8 address lines A[7:0] transmitted during the address phase of an EPI transfer. This latch can be seen on the expansion board block diagram shown in Figure E-3. Figure E-3.
8-bit Latch This 8-bit latch is used to store the lower 8-bits of the address, which are transmitted during the address phase of an EPI transfer. The EPI must be configured in Host bus 8 mode 0 mode (HB8 ADMUX), with EPI30 configured as an Address Latch Enable (ALE) signal to control this latch. Flash Memory The Flash memory used is a 64 Mbit, 90-nsec Spansion S29GL064N90TFI040. This 8/16 bit memory is used in 8-bit mode. Note that MA27 is used as a chip select signal for this memory.
Stellaris® LM3S9B96 Development Kit User’s Manual Memory Map The DK-LM3S9B96-EXP-FS8 expansion board memory map is shown in Table E-1 and Table E-2 shows the LCD Latch register. Table E-1. Flash and SRAM Memory Expansion Board Memory Map Device A[27:26] A[2:0] FLASH 0X XXX Flash memory (8 Megabytes) R/W 0x6000.0000 SRAM 10 XXX SRAM (1 Megabyte) R/W 0x6800.0000 11 000 LCD latch set R/W 0x6C00.0000 11 001 LCD latch clear R/W 0x6C00.
Component Locations Figure E-4 shows the details of the component locations. Figure E-4.
Flash, SRAM 1 2 3 4 5 Revision History MAD[7..0] Revision MA[27..0] J1 3.3V A R5 2.80k R6 2.80k MAD2 MAD3 MAD4 MAD5 PC4/EPI2 PC5/EPI3 PC6/EPI4 PC7/EPI5 U5 1 2 3 7 4 A0 SCL A1 SDA A2 WP GND VCC 6 5 I2CSCL I2CSDA 3.3V 5V 3.3V 8 R1 CAT24C01 1K - 128X8 0 Note: R1 is not fitted C10 0.
LCD Interface 1 2 3 4 5 6 A A MAD[7..0] MA[27..0] MAD[7..0] MA[27..0] L_D[7..0] LCD_DECODE CPLD U6 MAD0 MAD1 MAD2 MAD3 MAD4 MAD5 MAD6 MAD7 MA24 MA25 MA26 MA27 B ALE MOEn MWEn TP1 TP2 TP3 TP4 TP5 TP6 44 45 46 47 48 2 3 4 7 8 9 10 14 15 16 17 43 18 19 42 CPLD_TCK CPLD_TMS CPLD_TDI CPLD_TDO 1 11 25 35 3.
A P P E N D I X F Stellaris® LM3S9B96 FPGA Expansion Board This chapter describes the FPGA expansion board for the DK-LM3S9B96 development board.The FPGA expansion board provides a quick start platform to evaluate the capabilities of the Stellaris External Peripheral Interface (EPI) using the highly integrated DK-LM3S9B96 development platform. This combination adds full-screen motion video to the powerful, easy-to-use StellarisWare® GUI tools. Figure F-1 shows a photo of the FPGA expansion board.
Widget-based touchscreen user interface Screen capture to SDCard or USB stick in Windows bitmap (BMP) format Brightness, saturation, tint/hue, and sharpness picture controls Mirror/Flip/Normal Picture controls Installation To install the expansion board on the DK-LM3S9B96 development board, do the following: 1. Remove the LM3S9B96 FPGA memory expansion board from the antistatic bag. 2. On the DK-LM3S9B96 board, remove any installed board on EPI connector J2. 3.
Stellaris® LM3S9B96 Development Kit User’s Manual Figure F-2.
Hardware Description The FPGA expansion board is designed for use with the Stellaris EPI module. Figure F-3 shows a simplified system block diagram. Components of the default FPGA board are shown in half-tone outline. Figure F-3. FPGA Expansion Board Block Diagram FPGA The FPGA expansion board features a Xilinx Spartan 3e FPGA, which interfaces to the Stellaris® microcontroller through its EPI port and acts as a crossbar to the rest of the peripherals.
Stellaris® LM3S9B96 Development Kit User’s Manual Test Port Eight uncommitted FPGA pins are brought to test pads. Five of the FPGA pins can only be used as inputs. The remaining three FPGA pins can be used as inputs or outputs. Camera Connector The camera is hosted by the FPC Connector P1 located to the left of the FPGA. To insert or remove the camera, first open the latch by grasping either side of the connector and gently lifting straight up. With the latch open, the camera moves easily; do not force.
EPIConfigGPModeSet(EPI0_BASE, (EPI_GPMODE_DSIZE_16 | EPI_GPMODE_ASIZE_12 | EPI_GPMODE_WORD_ACCESS | EPI_GPMODE_READWRITE | EPI_GPMODE_READ2CYCLE | EPI_GPMODE_CLKPIN | EPI_GPMODE_RDYEN ), 0, 0); EPIAddressMapSet(EPI0_BASE, EPI_ADDR_PER_SIZE_64KB | EPI_ADDR_PER_BASE_A); //16 Bit data //12 Bit address //Use Word Access Mode //Use read and write strobe pins //Reads take two cycles //EPI outputs clock to peripheral //Peripheral emits a ready signal //Not using frame signal, so ignore //Not using clock enable, s
Stellaris® LM3S9B96 Development Kit User’s Manual Table F-1.
System Control Register The System Control register provides access to configuration bits for the video capture and display system. It is implemented as a read-modify-write register and includes LCD and capture modes. Table F-3. System Control Register SYSCTRL: 0xA000.
Stellaris® LM3S9B96 Development Kit User’s Manual Interrupt Enable Register The Interrupt Enable register masks or enables interrupts from the FPGA to the Stellaris LM3S9B96 microcontroller. Masked interrupts will not assert the IRQ line, but they will still appear in the Interrupt Status Register. Table F-4. Interrupt Enable Register IRQEN: 0xA000.
VCFEI Video capture frame end interrupt. Clear the interrupt by setting the corresponding bit to 1. Setting the bit to 0 has no effect. VRMI Video capture row match interrupt. Clear the interrupt by setting the corresponding bit to 1. Setting the bit to 0 has no effect. LTSI LCD transfer start interrupt. Clear the interrupt by setting the corresponding bit to 1. Setting the bit to 0 has no effect. LTEI LCD transfer end interrupt. Set to 1 to clear the corresponding bit.
Stellaris® LM3S9B96 Development Kit User’s Manual Table F-7. LCD Control Register LCDCTRL: 0xA000.0012 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 R R R R R R R R 7 6 5 4 3 2 1 0 BL RST YN XN R/2 R/W R/W R/W 0 R R R R Bit Name Description XN LCD panel touchscreen X control. When set to 0, the LCD Xn signal is set to 0. When set to 1, the LCD Xn signal is tri-stated. YN LCD panel touchscreen Y control. When set to 0, the LCD Yn signal is set to 0.
LCD Video Memory Address Low Register The LVML register provides a pointer to the start of video data for transfer to the LCD. This contains the lower 16-bits of the address. LCD Video Memory Address High Register The LVMH register provides a pointer to the start of video data for transfer to the LCD. This contains the higher 16-bits of the address. LCD Video Memory Stride Register The LVMS register specifies the number of bytes between the first pixels on adjacent rows in LCD video memory.
Stellaris® LM3S9B96 Development Kit User’s Manual Memory Port Register The MPORT register allows sequential video/graphics memory plane access. A write (read) to this port generates a memory write (read) to the memory location calculated as follows: Mem address = {MPH:MPL} + MPR x MPS + MPC. After the transfer, if the MPC is not at the last pixel of the row, it automatically increments by 1. If the MPC is at the last pixel of the row, it sets to 0 and the MPR is incremented by MPS.
Installing the Software To install the software, do the following: 1. Plug the provided cable into J4 (on the right side of the board), taking care to ensure proper alignment and orientation. The silk-screened signal names should match, with the exception that 2.5 V corresponds to VDD. When correctly aligned, the “JTAG-SPI Full Speed" text should face in toward the FPGA. Modifying the Default Image This section provides the descriptions for the default FPGA image blocks.
Stellaris® LM3S9B96 Development Kit User’s Manual EPI Signal Descriptions Table F-8 provides the EPI module’s signal descriptions. Table F-8.
Component Locations Figure F-5 shows the details of the component locations from the top view and Figure F-6 shows the details of the component locations from the bottom view. Figure F-5.
Stellaris® LM3S9B96 Development Kit User’s Manual Figure F-6.
EPI, LCD, Camera I/F 1 2 3 4 5 6 3.3V Revision History EPI[31..0] R2 2.80k U1A J1 U9 A 1 2 3 7 4 6 5 A0 SCL A1 SDA A2 WP GND VCC EPI2 EPI3 EPI4 EPI5 3.3V 8 CAT24C01 1K - 128X8 PC4/EPI2 PC5/EPI3 PC6/EPI4 PC7/EPI5 C49 0.1uF I2CSCL I2CSDA 2.8VD R19 2.80k R20 2.80k 3.3V EPI31 EPI18 EPI15 EPI12 3.3V 3.3V 5V PG7/EPI31 PJ2/EPI18 PF5/EPI15 PF4/EPI12 EPI9 EPI8 EPI11 EPI26 PE1/EPI9 PE0/EPI8 PH5/EPI11 PH6/EPI26 U7 B 3 4 8 1 SCL1 SDA1 EN GND 6 5 SCL2 SDA2 2.
SRAM, Power, JTAG 1 2 3.3V 3 4 5 6 2.5V U1G 100 79 A 28 13 49 64 42 VCCO_0 VCCO_0 137 65 30 102 VCCAUX VCCAUX VCCAUX VCCAUX VCCO_1 VCCO_1 80 9 45 115 VCCINT VCCINT VCCINT VCCINT VCCO_3 VCCO_3 U1D 1.2V VCCO_2 VCCO_2 VCCO_2 C25 0.1uF C26 0.1uF C27 0.1uF C28 0.1uF C29 0.1uF C30 0.1uF C31 0.1uF C32 0.1uF BANK 3 138 121 C46 10uF XC3S100E-4TQG144C C33 0.1uF C34 0.1uF C35 0.1uF C36 0.1uF C37 0.1uF C38 0.
September 5, 2010
A P P E N D I X G Stellaris® LM3S9B96 EM2 Expansion Board This document describes the Stellaris® LM3S9B96 EM2 Expansion Board (DK-LM3S9B96-EM2) for the DK-LM3S9B96 development board. The EM2 expansion board provides a transition between the Stellaris External Peripheral Interface (EPI) connector and the RF Evaluation Module (EM) connector. The DK-LM3S9B96-EM2 enables wireless application development using Low Power RF (LPRF) and RF ID evaluation modules on the Stellaris DK-LM3S9B96 platform. Figure G-1.
2. On the DK-LM3S9B96 board (shown in Figure G-2), confirm that shunt jumpers on JP16-JP31 (B) are installed to enable the LCD touch screen. JP39 (C), the leftmost jumper indicated, should remain uninstalled. Figure G-2. Removing EPI Board from DK-LM3S9B96 Development Board (A) Remove board (C) Leave JP39 uninstalled (B) Confirm shunt jumpers (JP16-JP31) installed 3.
Stellaris® LM3S9B96 Development Kit User’s Manual Figure G-3. EM2 Expansion Board Bottom side of EM2 module Male EPI expansion connector 4. Press firmly downward until the board snaps in place. Figure G-4.
Installation of EM Modules onto the EM2 Expansion Board The EM2 expansion board has a primary EM header (MOD1) and a secondary EM header (MOD2) as indicated on the silk screen (see Figure G-5). The secondary EM header is rotated 180 degrees from the primary EM header. There are many types of EM modules that can be installed onto the EM2 expansion board.
Stellaris® LM3S9B96 Development Kit User’s Manual 4. Use a slight pressure to seat the EM module firmly on the EM2 expansion board. See Figure G-6 on page 73 for fully assembled DK-LM3S9B96 board with EM2 expansion board and wireless EM module. Figure G-6.
Hardware Description The block diagram for the EM2 expansion board is shown in Figure G-7. Figure G-7. EM2 Expansion Board Block Diagram 32 KHZ OSC EPI Connector +3.3 V MOD_I2C UART1 SPI MOD1 SPI_CS /4 /4 AD_I2C PRIMARY EM HEADER (MOD1) /4 I2S Audio Header GPIO Analog Audio Header +3. 3 V I2C UART I2S Audio Header SECONDARY EM SPI HEADER (MOD2) SHUT MOD2 SPI_CS MOD2 SHUTDOWN MOD2 GPIO I2C UART SPI SHUT DOWN MOD1 SHUTDOWN MOD1 GPIO SDIO Header +3.
Stellaris® LM3S9B96 Development Kit User’s Manual The primary EM header contains one GPIO connection used to shut down and/or reset the EM module. The actual function depends on the EM module installed. The MODx_nSHUTD signal is pulled up to 3.3 V on the EM2 adapter. Each header has its own MODx_nSHUTD signal. The primary EM header contains additional features not found on the secondary EM header including a 32-KHz oscillator input and a header for a 4-bit SDIO module.
Table G-1.
Stellaris® LM3S9B96 Development Kit User’s Manual Component Locations Figure G-8 shows the details of the component locations. Figure G-8.
EM2 Expansion Board 5 4 3 2 1 Primary EM header +3.3V +3.3V INSTALL RESISTOR R7 WHEN 2nd MODULE NEEDS SLOW CLK. SEC_MOD_SCLK 32KHz Clock R7 0 D R8 OSC1 1 2 0 OUT GND 4 3 VCC EN MC_32.768kHz C2 10000pF DNI C3 10nF C4 1uF MOD1_SDIO_D0 MOD_UART_CTS MOD1_SDIO_D1 MOD_SLOWCLK MOD1_SDIO_D2 MOD_UART_RX MOD1_SDIO_D3 MOD_UART_TX MOD1_GPIO0 MOD_I2C_SDA MOD1_GPIO1 MOD_I2C_SCL SPI_CS1 MOD1_SDIO_CLK SPI_CLK MOD1_SDIO_CMD SPI_MOSI Header_1x8_100_430L +3.
A P P E N D I X H References In addition to this document, the following references are included on the Stellaris DK-LM3S9B96 Development Kit Documentation and Software CD and are also available for download at www.ti.com/stellaris: Stellaris LM3S9B96 Microcontroller Data Sheet Kitronix LCD Data Sheet StellarisWare Driver Library StellarisWare Driver Library User’s Manual, publication number SW-DRL-UG Additional references include: FT2232D Dual USB/UART FIFO IC Data sheet, version 0.
September 5, 2010
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
