Static RAM Specification Sheet

CY62128EV30
Document #: 38-05579 Rev. *D Page 7 of 11
Figure 5. Write Cycle No. 2 (CE1 or CE2 controlled)
[10, 14, 18, 19]
Figure 6. Write Cycle No. 3 (WE controlled, OE LOW)
[10, 19]
Switching Waveforms (continued)
t
WC
DATA VALID
t
AW
t
SA
t
PWE
t
HA
t
HD
t
SD
t
SCE
ADDRESS
CE
DATA IO
WE
DATA VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
ADDRESS
CE
WE
DATA IO
NOTE
20
Table 2. Truth Table for CY62128EV30
CE
1
CE
2
WE OE Inputs/Outputs Mode Power
H X X X High Z Deselect/Power Down Standby (I
SB
)
X L X X High Z Deselect/Power Down Standby (I
SB
)
L H H L Data Out Read Active (I
CC
)
L H H H High Z Output Disabled Active (I
CC
)
L H L X Data in Write Active (I
CC
)
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