Static RAM Specification Sheet
CY62128EV30
Document #: 38-05579 Rev. *D Page 5 of 11
Data Retention Waveform
[10]
Switching Characteristics
(Over the Operating Range)
[10, 11]
Parameter Description
45 ns (Ind’l/Auto-A) 55 ns (Auto-E)
Unit
Min Max Min Max
Read Cycle
t
RC
Read Cycle Time 45 55 ns
t
AA
Address to Data Valid 45 55 ns
t
OHA
Data Hold from Address Change 10 10 ns
t
ACE
CE LOW to Data Valid 45 55 ns
t
DOE
OE LOW to Data Valid 22 25 ns
t
LZOE
OE LOW to Low Z
[12]
55ns
t
HZOE
OE HIGH to High Z
[12,13]
18 20 ns
t
LZCE
CE
LOW to Low Z
[12]
10 10 ns
t
HZCE
CE HIGH to High Z
[12, 13]
18 20 ns
t
PU
CE LOW to Power Up
00ns
t
PD
CE HIGH to Power Up 45 55 ns
Write Cycle
[14]
t
WC
Write Cycle Time 45 55 ns
t
SCE
CE LOW to Write End 35 40 ns
t
AW
Address Setup to Write End 35 40 ns
t
HA
Address Hold from Write End 0 0 ns
t
SA
Address Setup to Write Start 0 0 ns
t
PWE
WE Pulse Width
35 40 ns
t
SD
Data Setup to Write End 25 25 ns
t
HD
Data Hold from Write End 0 0 ns
t
HZWE
WE LOW to High Z
[12, 13]
18 20 ns
t
LZWE
WE HIGH to Low Z
[12]
10 10 ns
V
CC(min)
V
CC(min)
t
CDR
V
DR
> 1.5V
DATA RETENTION MODE
t
R
V
CC
CE
Notes
10. CE
is the logical combination of CE
1
and CE
2
. When CE
1
is LOW and CE
2
is HIGH, CE is LOW; when CE
1
is HIGH or CE
2
is LOW, CE is HIGH.
11. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of V
CC(typ)
/2, input
pulse levels of 0 to V
CC(typ)
, and output loading of the specified I
OL
/I
OH
as shown in the “AC Test Loads and Waveforms” on page 4.
12. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
13. t
HZOE
, t
HZCE
, and t
HZWE
transitions are measured when the output enter a high impedance state.
14. The internal write time of the memory is defined by the overlap of WE
, CE = V
IL
. All signals must be ACTIVE to initiate a write and any of these signals can
terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
[+] Feedback