nvSRAM Specification Sheet
CY14B104L, CY14B104N
Document #: 001-07102 Rev. *L Page 14 of 25
Hardware STORE Cycle
Parameters Description
CY14B104L/CY14B104N
Unit
Min Max
t
PHSB
Hardware STORE Pulse Width 15 ns
t
HLBL
Hardware STORE LOW to STORE Busy 500 ns
Switching Waveforms
Figure 14. Hardware STORE Cycle
[21]
Figure 15. Soft Sequence Processing
[27, 28]
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Notes
27. This is the amount of time it takes to take action on a soft sequence command. V
CC
power must remain HIGH to effectively register command.
28. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.
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