Specifications

ManualsBrandsCypress ManualsComputer HardwareCY14B101P

CY14B101P

Document Number: 001-44109 Rev. *O Page 8 of 36

SPI Operating Features

Power-Up

Power-up is defined as the condition when the power supply is

turned on and V

crosses V

SWITCH

voltage. During this time,

the CS

must be enabled to follow the V

voltage. Therefore, CS

must be connected to V

through a suitable pull-up resistor. As

a built in safety feature, CS

is both edge sensitive and level

sensitive. After power-up, the device is not selected until a falling

edge is detected on CS. This ensures that CS is HIGH, before

going LOW to start the first operation.

As described earlier, nvSRAM performs a Power-Up RECALL

operation after power-up and therefore, all memory accesses are

disabled for t

duration after power-up. The HSB pin can be

probed to check the ready/busy status of nvSRAM after

power-up.

Power-On Reset

A power-on reset (POR) circuit is included to prevent inadvertent

writes. At power-up, the device does not respond to any

instruction until the V

reaches the POR threshold voltage

SWITCH

). After V

transitions the POR threshold, the device

is internally reset and performs an Power-Up RECALL operation.

During Power-Up RECALL all device accesses are inhibited.

The device is in the following state after POR:

■ Deselected (after power-up, a falling edge is required on CS

before any instructions are started).

■ Standby power mode

■ Not in the HOLD Condition

■ Status Register state:

❐ Write Enable (WEN) bit is reset to 0.

❐ WPEN, BP1, BP0 unchanged from previous STORE

operation

❐ Don’t care bits 4-6 are reset to 0.

The WPEN, BP1, and BP0 bits of the Status Register are

nonvolatile bits and remain unchanged from the previous

STORE operation.

Before selecting and issuing instructions to the memory, a valid

and stable V

voltage must be applied. This voltage must

remain valid until the end of the instruction transmission.

Power-Down

At power-down (continuous decay of V

), when V

drops from

the normal operating voltage and below the V

SWITCH

threshold

voltage, the device stops responding to any instruction sent to it.

If a write cycle is in progress and the last data bit D0 has been

received when the power goes down, it is allowed t

DELAY

time to

complete the write. After this, all memory accesses are inhibited

and a conditional AutoStore operation is performed (AutoStore is

not performed if no writes have happened since last RECALL

cycle). This feature prevents inadvertent writes to nvSRAM from

happening during power-down.

However, to avoid the possibility of inadvertent writes during

power-down, ensure that the device is deselected and is in

standby power mode, and the CS

follows the voltage applied on

Active Power and Standby Power Modes

When CS is LOW, the device is selected and is in the active

power mode. The device consumes I

current, as specified in

DC Electrical Characteristics on page 24. When CS

is HIGH, the

device is deselected and the device goes into the standby power

mode if a STORE or RECALL cycle is not in progress. If a

STORE/RECALL cycle is in progress, the device goes into the

standby power mode after the STORE/RECALL cycle is

completed. In the standby power mode the current drawn by the

device drops to I

SPI Functional Description

The CY14B101P uses an 8-bit instruction register. Instructions

and their operation codes are listed in Table 1. All instructions,

addresses, and data are transferred with the MSB first and start

with a HIGH to LOW CS

transition. There are, in all, 12 SPI

instructions that provide access to most of the functions in

nvSRAM. Further, the WP, HOLD and HSB pins provide

additional functionality driven through hardware.

The SPI instructions in CY14B101P are divided based on their

functionality in the following types:

❐ Status Register Access: RDSR and WRSR instructions

❐ Write protection functions: WREN and WRDI instructions

along with WP pin and WEN, BP0 and BP1 bits

❐ SRAM memory access: READ and WRITE instructions

❐ RTC access: RDRTC and WRTC instructions

❐ nvSRAM special instructions: STORE, RECALL, ASENB,

and ASDISB

Table 1. Instruction Set

Instruction