Specifications

CY14B101P
Document Number: 001-44109 Rev. *O Page 23 of 36
0x02
Alarm - Seconds
D7 D6 D5 D4 D3 D2 D1 D0
M 10s alarm seconds Alarm seconds
Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value.
M Match. When this bit is set to 0, the seconds value is used in the alarm match. Setting this bit to 1 causes the match
circuit to ignore the seconds value.
0x01
Time Keeping - Centuries
D7 D6 D5 D4 D3 D2 D1 D0
10s centuries Centuries
Contains the BCD value of centuries. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble
contains the upper digit and operates from 0 to 9. The range for the register is 0-99 centuries.
0x00
Flags
D7 D6 D5 D4 D3 D2 D1 D0
WDF AF PF OSCF 0 CAL W R
WDF Watchdog timer flag. This read only bit is set to ‘1’ when the watchdog timer is allowed to reach 0 without being reset
by the user. It is cleared to ‘0’ when the flags register is read or on power-up
AF Alarm flag. This read only bit is set to ‘1’ when the time and date match the values stored in the alarm registers with
the match bits = ‘0’. It is cleared when the flags register is read or on power-up.
PF Power fail flag. This read only bit is set to ‘1’ when power falls below the power fail threshold V
SWITCH
. It is cleared to
‘0’ when the flags register is read or on power-up.
OSCF Oscillator fail flag. Set to ‘1’ on power-up if the oscillator is enabled and not running in the first 5 ms of operation. This
indicates that RTC backup power failed and clock value is no longer valid. This bit survives the power cycle and is never
cleared internally by the chip. The user must check for this condition and write '0' to clear this flag. When user resets
OSCF flag bit, the bit will be updated after t
RTCp
time.
CAL Calibration mode. When set to ‘1’, a 512 Hz square wave is output on the INT pin. When set to ‘0’, the INT pin resumes
normal operation. This bit defaults to 0 (disabled) on power-up.
W Write enable: Setting the ‘W’ bit to ‘1’ freezes updates of the RTC registers. The user can then write to RTC registers,
alarm registers, calibration register, interrupt register and flags register. Setting the ‘W’ bit to ‘0’ causes the contents of
the RTC registers to be transferred to the time keeping counters if the time has changed. This transfer process takes
t
RTCp
time to complete. This bit defaults to 0 on power-up.
R Read enable: Setting ‘R’ bit to ‘1’, stops clock updates to user RTC registers so that clock updates are not seen during
the reading process. Set ‘R’ bit to ‘0’ to resume clock updates to the holding register. Setting this bit does not require
‘W’ bit to be set to ‘1’. This bit defaults to 0 on power-up.
Table 9. Register Map Detail (continued)
Not Recommended for New Designs