Specifications

CY14B101P
Document Number: 001-44109 Rev. *O Page 14 of 36
WRITE RTC (WRTC) Instruction
WRITE RTC (WRTC) instruction allows the user to modify the
contents of RTC registers. The WRTC instruction requires the
WEN bit to be set to '1' before it can be issued. If WEN bit is '0',
a WREN instruction needs to be issued before using WRTC.
Writing RTC registers requires the following sequence: After the
CS
line is pulled LOW to select a device, WRTC opcode is
transmitted through the SI line followed by eight address bits
identifying the register which is to be written to and one or more
bytes of data. WRTC allows burst mode write operation. When
writing more than one registers in burst mode, the address rolls
over to 0x00 after the last RTC address (0x0F) is reached.
Note that writing to RTC timekeeping and control registers
require the ‘W’ bit to be set to '1'. The values in these RTC
registers take effect only after the W bit is cleared to '0'. Write
Enable bit (WEN) is automatically cleared to ‘0’ after completion
of the WRTC instruction.
nvSRAM Special Instructions
CY14B101P provides four special instructions that allow access
to the nvSRAM specific functions: STORE, RECALL, ASDISB,
and ASENB. Table 6 lists these instructions.
Software STORE (STORE) instruction
When a STORE instruction is executed, CY14B101P performs a
Software STORE operation. The STORE operation is performed
irrespective of whether a write has taken place since the last
STORE or RECALL operation.
To issue this instruction, the device must be write enabled
(WEN bit = ‘1’).The instruction is performed by transmitting the
STORE opcode on the SI pin following the falling edge of CS
.
The WEN bit is cleared on the positive edge of CS
following the
STORE instruction.
Software RECALL (RECALL) instruction
When a RECALL instruction is executed, CY14B101P performs
a Software RECALL operation. To issue this instruction, the
device must be write enabled (WEN = ‘1’).
The instruction is performed by transmitting the RECALL opcode
on the SI pin following the falling edge of CS
. The WEN bit is
cleared on the positive edge of CS
following the RECALL
instruction.
AutoStore Enable (ASENB) instruction
The AutoStore Enable instruction enables the AutoStore on
CY14B101P. This setting is not nonvolatile and needs to be
followed by a STORE sequence if this is desired to survive the
power cycle.
To issue this instruction, the device must be write enabled
(WEN = ‘1’). The instruction is performed by transmitting the
ASENB opcode on the SI pin following the falling edge of CS
.
The WEN bit is cleared on the positive edge of CS
following the
ASENB instruction.
Figure 15. Write RTC (WRTC) Instruction Timing
CS
SCK
SO
012345 67
0
3
2
1
45 67012345 67
SI
Op-Code
000 1
00 1
0000
0
A3
A1A2
A0
4-bit Address
MSB
LSB
MSB LSB
Data
HI-Z
D0
D1
D2
D3
D4
D5
D6D7
Table 6. nvSRAM Special Instructions
Function Name Opcode Operation
STORE 0011 1100 Software STORE
RECALL 0110 0000 Software RECALL
ASENB 0101 1001 AutoStore Enable
ASDISB 0001 1001 AutoStore Disable
Figure 16. Software STORE Operation
0 0 1 1 1 1 0 0
CS
SCK
SI
SO
HI-Z
0 1 2 3 4 5 6 7
Figure 17. Software RECALL Operation
0 1 1 0 0 0 0 0
CS
SCK
SI
0 1 2 3 4 5 6 7
SO
HI-Z
Not Recommended for New Designs