Datasheet

CY8C20xx6A/H CapSense Design Guide Doc. No. 001-65973 Rev. *A 49
implies that ,to use sleep mode and the PLL, the software must be able to execute at 3 MHz. A simple write to the
OSC_CR0 register can reduce CPU speed. However, this register just sets a divider of SYSCLK, which means that
the CPU speed will vary between part families with different SYSCLKs. Typically, SYSCLK is 24 MHz
OSC_CR0 &= 0xf8; // CPU = 3 IMO = 24
6.2.2 Execution of Global Interrupt Enable
It is undesirable to get an interrupt on the instruction boundary of writing the SLEEP bit. This could cause all firmware
preparations for going to sleep to be bypassed, if a sleep command is executed on a return from interrupt (reti)
instruction. To prevent this, interrupts are temporarily disabled before sleep preparations and then re-enabled before
going to sleep. Because of the timing of the Global Interrupt instruction, an interrupt cannot occur during the next
instruction, which in this case is setting the SLEEP bit.
6.2.3 I
2
There are a few complications using an I
C Slave with Sleep Mode
2
C Slave in sleep mode. Because the IMO and CPU are shut off during
sleep, there is no processing within the PSoC. The problem arises with the I
2
C address. When an I2C START
condition is sent to a particular address, the PSoC cannot process the address and therefore responds with a NAK. A
typical workaround is to set up falling edge interrupts on either the clock or data lines of the I
2
C bus. The master can
then send a dummy START condition to wake up the PSoC. There is some lag time between waking up and being
able to process an I
2
C address, so the master may need to delay up to 200 µs before the next transmission or
continue to send until an ACK is received. This solution has a second problem in that the PSoC will wake up on any
I
2
6.2.4 Sleep Timer
C falling edge traffic, which causes more total active time and higher sleep currents. Another solution is to use a
third GPIO pin to wake up the PSoC and then send the initial START condition after the appropriate delay time.
The PSoC offers a sleep timer and a sleep timer user module. These are used while PSoC is asleep and both
perform similar functions. The actual sleep timer runs off of the internal low-speed oscillator, which is never turned off.
At selectable intervals of 1 Hz, 8 Hz, 64 Hz, and 512 Hz, the timer generates an interrupt. It is often useful to
periodically wake the PSoC up to do some processing or check for activity. An example of this would be to
periodically wake up to scan a sensor. The sleep timer user module uses the sleep timer to generate some additional
functionality. This functionality includes a background tick counter to generate periodic interrupts, a delay function for
program loops, a settable down counter, and a loop governor to control loop time. A simple block diagram for this
functionality is shown below in Figure 6-1. .
Figure 6-1. Sleep Timer User Module Block Diagram