Datasheet

CY8C20xx6A/H CapSense Design Guide Doc. No. 001-65973 Rev. *A 48
6.1.2 Putting it All Together
The following code is a sample of a typical sleep preparation sequence for a 28-pin part. In this sequence, interrupts
are disabled, the analog circuitry is turned off, all drive modes are set to Analog HI-Z, and interrupts are re-enabled.
void PSoC_Sleep(void){
M8C_DisableGInt;
ARF_CR &= 0xf8; // analog blocks Off
ABF_CR0 &= 0xc3; // analog buffer off
PRT0DM0 = 0x00; // port 0 drives
PRT0DM1 = 0xff;
PRT0DM2 = 0xff;
PRT1DM0 = 0x00; // port 1 drives
PRT1DM1 = 0xff;
PRT1DM2 = 0xff;
PRT2DM0 = 0x00; // port 2 drives
PRT2DM1 = 0xff;
PRT2DM2 = 0xff;
M8C_EnableGInt;
M8C_Sleep;
}
6.1.3 Sleep Mode Complications
The PSoC can exit sleep either from a reset or through an interrupt. There are three types of resets within the PSoC:
External Reset, Watch Dog Reset, and Power On Reset. Any of these resets takes the PSoC out of sleep mode, and
once the reset deasserts, the PSoC begins executing code starting at Boot.asm. Available interrupts to wake the
PSoC are: Sleep Timer, Low Voltage Monitor, GPIO, Analog Column, and Asynchronous. Sleep mode complications
arise when using interrupts to wake the PSoC or attempting digital communication while asleep. These
considerations are discussed in detail in the following sections.
6.1.4 Pending Interrupts
If an interrupt is pending, enabled, and scheduled to take after a write to the SLEEP bit in the CPU_SCR0 register,
the system will not go to sleep. The instruction still executes, but the PSoC does not set the SLEEP bit. Instead, the
interrupt is serviced which effectively causes the PSoC to ignore the sleep instruction. To avoid this, interrupts should
be globally disabled while sleep preparation occurs and then re-enabled just before writing the SLEEP bit.
6.1.5 Global Interrupt Enable
The Global Interrupt Enable register (CPU_F) need not to be enabled to wake the PSoC from interrupts. The only
requirement to wake up from a Sleep by an interrupt is to use the correct interrupt mask within the INT_MSKx
registers, as in the example below. If global interrupts are disabled, the ISR that wakes the PSoC is not executed but
the PSoC still exits sleep mode.
In this case, you must manually clear the pending interrupt or enable global interrupts to allow the ISR to be serviced.
Interrupts are cleared within the INT_CLRx registers.
//Set Mask for GPIO Interrupts
M8C_EnableIntMask(INT_MSK0, INT_MSK0_GPIO)
// Clear Pending GPIO Interrupt
INT_CLR0 &= 0x20;
6.2 Post Wakeup Execution Sequence
If the PSoC is awakened through a reset, then execution starts at the beginning of the boot code. If the PSoC is
woken up by an interrupt service routine, the first instruction to execute is the one immediately following the sleep
instruction. This is because the instruction immediately following the sleep instruction is prefetched before the PSoC
is fully asleep. Therefore, if global interrupts are disabled, the instruction execution will continue where it left off
before sleep was initiated.
6.2.1 PLL Mode Enabled
If PLL mode is enabled, the CPU frequency must be reduced to the minimum of 3 MHz before going to sleep. This is
because the PLL always overshoots as it attempts to relock after the PSoC wakes up and is re-enabled. Additionally,
you should wait 10 ms after wakeup before normal CPU operation commences to ensure proper execution. This