Specifications

ManualsBrandsCypress Semiconductor ManualsComputer equipmentSL811HS

SL811HS

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

Document #: 38-08008 Rev. *A Revised March 14, 2002

SL811HS

Embedded USB Host/Slave Controller

Summary of content (29 pages)

PAGE 1
SL811HS SL811HS Embedded USB Host/Slave Controller Cypress Semiconductor Corporation Document #: 38-08008 Rev.
PAGE 2
SL811HS TABLE OF CONTENTS 1.0 CONVENTIONS .............................................................................................................................. 4 2.0 DEFINITIONS .................................................................................................................................. 4 3.0 REFERENCES ................................................................................................................................ 4 4.0 INTRODUCTION .............................
PAGE 3
SL811HS License Agreement Use of this document and the intellectual properties contained herein indicates acceptance of the following License Agreement.
PAGE 4
SL811HS 1.0 Conventions 1,2,3,4 Numbers without annotations are decimals. Dh, 1Fh, 39h Hexadecimal numbers are followed by an “h.” 0101b, 010101b Binary numbers are followed by a “b.” bRequest, n Words in italics indicate terms defined by USB Specification or by this Specification. 2.0 Definitions USB Universal Serial Bus SL811HS The SL811HS is a Cypress USB Host/Slave Controller, providing multiple functions on a single chip.
PAGE 5
SL811HS Master/Slave Controller INTERRUPT CONTROLLER INTR RAM D+ D- SERIAL USB INTERFACE Root-HUB XCVRS ENGINE BUFFERS & CONTROL REGISTERS PROCESSOR CLOCK GENERATOR INTERFACE nWR nRD nCS nRST D0-7 X1 X2 Figure 4-1. SL811HS USB Host/Slave Controller Functional Block Diagram 4.2 SL811HS Host or Slave Mode Selection [Master/Slave Mode] SL811HS can work in two modes—host or slave. For slave-mode operation and specification, please refer to the SL811S specification.
PAGE 6
SL811HS 4.4 Data Port, Microprocessor Interface The SL811HS microprocessor interface provides an 8-bit bidirectional data path along with appropriate control lines to interface to external processors or controllers. The control lines, Chip Select, Read and Write input strobes and a single address line, A0, along with the 8-bit data bus, support programmed I/O or memory mapped I/O designs.
PAGE 7
SL811HS X1 X2 Rf 1M Rs X1 100 48 MHz, series, 20-pF load Cbk 0.01 µF Cin 22 pF Lin 2.2 µH Cout 22 pF Figure 4-2. Full-Speed 48-MHz Crystal Circuit X1 X2 Rf 1M Rs 100 X1 12 MHz , series, 20-pF load Cin Cout 22 pF 22 pF Figure 4-3. Optional 12-MHz Crystal Circuit Note: 1. CM (Clock Mode) pin of the SL811HS should be tied to GND when 48-MHz Xtal circuit or 48-MHz clock source is used. Document #: 38-08008 Rev.
PAGE 8
SL811HS 4.7.1 Typical Crystal Requirements The following are examples of “typical requirements”. Please note that these specifications are generally found as standard crystal values and are therefore less expensive than custom values. If crystals are used in series circuits, load capacitance is not applicable. Load capacitance of parallel circuits is a requirement.
PAGE 9
SL811HS SL11H (hex) Address SL811HS (hex) Address USB-A Host Control Register 00H 00H USB-A Host Base Address 01H 01H USB-A Host Base Length 02H 02H USB-A Host PID, Device Endpoint (Write)/USB Status (Read) 03H 03H USB-A Host Device Address (Write)/Transfer Count (Read) 04H 04H Control Register1 05H 05H Interrupt Enable Register 06H 06 H Reserved Register Reserved Reserved USB-B Host Control Register Reserved 08H USB-B Host Base Address Reserved 09H USB-B Host Base Length Re
PAGE 10
SL811HS 5.2.
PAGE 11
SL811HS 5.2.4 SOF Packet Generation The SL811HS automatically computes CRC5 by hardware. No CRC or SOF is required to be generated by external firmware for SL811HS. 5.2.5 USB-A/USB-B Host Base Address [01H, 09H] The USB-A/USB-B Base Address is a Pointer to the SL811HS memory buffer location for USB reads and writes. When transferring data OUT (Host to Device), the USB-A and USB-B can be set up prior to setting ARM on the USB-A or USB-B Host Control register. See the software implementation example. 5.2.
PAGE 12
SL811HS 5.2.8 USB-A/USB-B Host Transfer Count Register (Read), USB Address (Write) [04H, 0CH] This register has two functions. When read, this register contains the number of bytes left over (from “Length” field) after a packet is transferred. If an overflow condition occurs, i.e., the received packet from slave USB device was greater than the Length field specified, a bit is set in the Packet Status Register indicating the condition.
PAGE 13
SL811HS 5.3.2 J-K Programming States [bits 3 and 4 of Control Register 05H] The J-K force state control and USB Engine Reset bits can be used to generate USB reset condition on the USB. Forcing K-state can be used for Peripheral device remote wake-up, Resume and other modes. These two bits are set to zero on power-up. 5.3.
PAGE 14
SL811HS 5.3.6 USB Address Register, Reserved, Address [07H] This register is reserved for the device USB Address in Slave operation. It should not be written by the user. 5.3.7 Interrupt Status Register, Address [0DH] The ISR is a Read/Write register providing interrupt status. Interrupts can be cleared by writing to this register. To clear a specific interrupt, the register is written with corresponding bit set to “1.
PAGE 15
SL811HS 5.3.9 SOF Counter HIGH/Control2 Register, Address [0FH, READ/WRITE] When writing to this register the bits definition are defined as follows. Bit Position Bit Name Function 0–5 SOF HIGH Counter Register Write a value or read it back to SOF HIGH Counter Register 6 SL811HS D+/D– Data Polarity Swap Write/Read, set “1” change polarity, “0” no change of polarity 7 SL811HS Master/Slave selection Write/Read, “1” is master, else Slave Note.
PAGE 16
SL811HS 6.0 SL811HS and SL811HST-AC Physical Connections This part is offered in both a 28-pin PLCC package (SL811HS) and a 48-pin TQFP package (SL811HST-AC). 6.1 SL811HS Physical Connections 6.1.1 SL811HS Pin Layout Pins 2 and 3 should be No Connect in Host Mode. See Pin and Signal Description.
PAGE 17
SL811HS 6.1.3 SL811HS USB Host Controller Pins Description The SL811HS package is a 28-pin PLCC. The device requires 3.3 VDC. Average typical current consumption is less then 20 mA for 3.3V. Table 6-1. SL811HS Pin Assignments and Definitions Pin No. Pin Type Pin Name Pin Description 1 IN A0 A0 = “0.” Selects Address Pointer. Reg. Write Only. Selects Data Buffer or Register. R/W.[4] 2 IN nDACK DMA Acknowledge. An active LOW input used to interface to an external DMA controller.
PAGE 18
SL811HS The Diagram below illustrates a simple +3.3V voltage source. 9 8 6% 5 2KPV 1 = HQH U Y 1 &7 * 1 ' 6.1.4 9 9'' 6DP SOH 9'' *HQHUDWRU Package Markings (SL811HS) YYWW = Date code XXXX = Product code X.X = Silicon revision number Document #: 38-08008 Rev.
PAGE 19
SL811HS 6.2 SL811HST-AC Physical Connections 6.2.1 SL811HST-AC Pin Layout [16] NC nRD NC NC NC NC NC D7 VDD A0 M/SDD NC 37 1 36 48 NC NC NC NC nWR NC nCS D6 CM D5 SL811HST VDD1 Data+ D4 GND Data- D3 USBGnd D2 NC D1 NC NC NC 12 24 25 NC 13 NC NC nRST GND Clk/X1 VDD D0 INTRQ X2 NC NC NC Figure 6-2. SL811HST-AC USB Host/Slave Controller Pin Layout 6.2.2 Mechanical Dimensions 48-Pin TQFP Note: 8. NC. Indicates No Connection. NC Pins should be left unconnected.
PAGE 20
SL811HS 6.2.3 SL811HST-AC USB Host Controller Pins Description The SL811HST-AC is packaged in a 48-pin TQFP. The device requires a 3.3VDC power source. The SL811HST-AC requires an external 12 or 48 MHz crystal or Clock. Table 6-2. SL811HST-AC Pin Assignments and Definitions Pin No. Pin Type Pin Name Pin Description 1 NC NC NC 2 NC NC NC 3 IN nWR Write Strobe Input. An active LOW input used with nCS to Write to registers/data memory. 4 IN nCS Active LOW SL811HST-AC Chip select.
PAGE 21
SL811HS Table 6-2. SL811HST-AC Pin Assignments and Definitions (continued) Pin No. Pin Type Pin Name Pin Description 33 BIDIR D6 Data 6. Microprocessor Data/(Address) Bus. 34 NC NC NC 35 NC NC NC 36 NC NC NC 37 NC NC NC 38 NC NC NC 39 BIDIR D7 Data 7. Microprocessor Data/(Address) Bus. 40 IN M/S Master/Slave Mode Select. “1” selects Slave. “0” = Master. 41 VDD +3.3 VDC 42 IN A0 43 IN nDACK DMA Acknowledge.
PAGE 22
SL811HS 7.0 Electrical Specifications 7.1 Absolute Maximum Ratings This section lists the absolute maximum ratings of the SL811HS. Stresses above those listed can cause permanent damage to the device. Exposure to maximum rated conditions for extended periods can affect device operation and reliability. Storage Temperature –40°C to 125°C Voltage on any pin with respect to ground –0.3V to 6.0V Power Supply Voltage (VDD) 4.0 V Power Supply Voltage (VDD1) 4.
PAGE 23
SL811HS 7.4 DC Characteristics Parameter Description Min. Typ. Max. VIL Input Voltage LOW –0.3 V 0.8V VIH Input Voltage HIGH (5V Tolerant I/O) 2.0 V 6.0V VOL Output Voltage LOW (IOL = 4 mA) VOH Output Voltage HIGH (IOH = –4 mA) 2.4 V IOH Output Current HIGH 4 mA IOL Output Current LOW 4 mA ILL Input Leakage ±1 µA Input Capacitance 10 pF CIN ICC [16] 0.4V Supply Current (VDD) inc USB @FS 21 mA 25 mA ICCsus1[17] ICCsus2[18] Supply Current (VDD) Suspend w/Clk & Pll Enb 4.
PAGE 24
SL811HS 7.6 Bus Interface Timing Requirements 7.6.1 I/O Write Cycle twrhigh twr nWR twasu twahld twdsu twdhld A0 Register or Memory Address D0-D7 twcsu twdsu twdhld DATA twshld nCS Tcscs See Note. I/O Write Cycle to Register or Memory Buffer Note: nCS an be held LOW for multiple Write cycles provided nWR is cycled. Parameter Description Min.
PAGE 25
SL811HS 7.6.2 I/O Read Cycle twr twrrdl nWR twahld twasu A0 trdp nRD twdhld twdsu Register or Memory Address D0-D7 tracc trdhld DATA trcsu trshld nCS Tcscs *Note I/O Read Cycle from Register or Memory Buffer Parameter Description Min.
PAGE 26
SL811HS 7.6.3 Reset Timing treset nRST tioact nRD or nWR RESET TIMING Parameter Description Min. tRESET nRst Pulse width 16 clocks tIOACT nRst HIGH to nRD or nWR active 16 clocks Typ. Max. Note. Clock is 48-MHz nominal. Document #: 38-08008 Rev.
PAGE 27
SL811HS 7.6.4 Clock Timing Specifications tclk tlow CLK thigh tfall trise CLOCK TIMING Parameter Description Min. Typ. 20.0 ns 20.8 ns Max. tCLK Clock Period (48 MHz) tHIGH Clock HIGH Time 9 ns 11 ns tLOW Clock LOW Time 9 ns 11 ns tRISE Clock rise Time 5.0 ns tFALL Clock fall Time 5.0 ns Clock Duty Cycle Document #: 38-08008 Rev.
PAGE 28
SL811HS 8.0 Package Diagrams 28-pin PLCC 48-pin TQFP Intel is a registered trademark of Intel Corporation. Torex is a trademark of Torex Semiconductors, Ltd. SL811HS is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-08008 Rev. *A Page 28 of 29 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice.
PAGE 29
SL811HS Document Title: SL811HS USB Host/Slave Controllers Hardware Specification Document Number: 38-08008 ECN NO. Issue Date ** 110850 12/14/01 BHA Converted to Cypress format from ScanLogic *A 112687 03/22/02 MUL 1) Changed power supply voltage to 4.0V in section 7.1 2) Changed value of twdsu in section 7.6.2 3) Changed max. power supply voltage to 3.45 V in section 7.2 4) Changed accuracy of adjustment in section 7.2 5) Changed bits 0 and 1 to reserved in section 5.3.