Specifications

ManualsBrandsCypress Semiconductor ManualsComputer equipmentPerform nvSRAM

CY14B256KA

256-Kbit (32 K × 8) nvSRAM with

Real Time Clock

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-55720 Rev. *H Revised July 3, 2013

256-Kbit (32 K × 8) nvSRAM with Real Time Clock

Features

■ 256-Kbit nonvolatile static random access memory (nvSRAM)

❐ 25 ns and 45 ns access times

❐ Internally organized as 32 K × 8 (CY14B256KA)

❐ Hands off automatic STORE on power-down with only a small

capacitor

❐ STORE to QuantumTrap nonvolatile elements is initiated by

software, hardware, or AutoStore on power-down

❐ RECALL to SRAM initiated on power-up or by software

■ High reliability

❐ Infinite Read, Write, and RECALL cycles

❐ 1 million STORE cycles to QuantumTrap

❐ 20 year data retention

■ Real time clock (RTC)

❐ Full-featured real time clock

❐ Watchdog timer

❐ Clock alarm with programmable interrupts

❐ Capacitor or battery backup for RTC

❐ Backup current of 0.35 µA (Typ)

■ Industry standard configurations

❐ Single 3 V +20%, –10% operation

❐ Industrial temperature

❐ 48-pin shrink small-outline package (SSOP)

❐ Pb-free and Restriction of hazardous substances (RoHS)

compliant

Functional Description

The Cypress CY14B256KA combines a 256-Kbit nonvolatile

static RAM with a full featured real time clock in a monolithic

integrated circuit. The embedded nonvolatile elements

incorporate QuantumTrap technology producing the world’s

most reliable nonvolatile memory. The SRAM is read and written

an infinite number of times, while independent nonvolatile data

resides in the nonvolatile elements.

The real time clock function provides an accurate clock with leap

year tracking and a programmable, high accuracy oscillator. The

alarm function is programmable for periodic minutes, hours,

days, or months alarms. There is also a programmable watchdog

timer for process control.

STORE/

RECALL

CONTROL

POWER

CONTROL

SOFTWARE

DETECT

STATIC RAM

ARRAY

512 X 512

QuantumTrap

512 X 512

STORE

RECALL

COLUMN IO

COLUMN DEC

ROW DECODER

INPUT BUFFERS

HSB

CAP

RTC

MUX

out

INT

RTCbat

RTCcap

Logic Block Diagram

Summary of content (28 pages)

PAGE 1
CY14B256KA 256-Kbit (32 K × 8) nvSRAM with Real Time Clock 256-Kbit (32 K × 8) nvSRAM with Real Time Clock Features ■ 256-Kbit nonvolatile static random access memory (nvSRAM) ❐ 25 ns and 45 ns access times ❐ Internally organized as 32 K × 8 (CY14B256KA) ❐ Hands off automatic STORE on power-down with only a small capacitor ❐ STORE to QuantumTrap nonvolatile elements is initiated by software, hardware, or AutoStore on power-down ❐ RECALL to SRAM initiated on power-up or by software ■ High reliability ❐ I
PAGE 2
CY14B256KA Contents Pinouts .............................................................................. 3 Pin Definitions .................................................................. 3 Device Operation .............................................................. 4 SRAM Read ................................................................ 4 SRAM Write ................................................................. 4 AutoStore Operation ....................................................
PAGE 3
CY14B256KA Pinouts Figure 1.
PAGE 4
CY14B256KA The CY14B256KA nvSRAM is made up of two functional components paired in the same physical cell. These are a SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to the SRAM (the RECALL operation). Using this unique architecture, all cells are stored and recalled in parallel.
PAGE 5
CY14B256KA it only when the STORE is complete. Upon completion of the STORE operation, the nvSRAM memory access is inhibited for tLZHSB time after HSB pin returns HIGH. Leave the HSB unconnected if it is not used. Hardware RECALL (Power-Up) During power-up or after any low power condition (VCC< VSWITCH), an internal RECALL request is latched. When VCC again exceeds the VSWITCH on powerup, a RECALL cycle is automatically initiated and takes tHRECALL to complete.
PAGE 6
CY14B256KA Table 1.
PAGE 7
CY14B256KA Real Time Clock Operation nvTIME Operation The CY14B256KA offers internal registers that contain clock, alarm, watchdog, interrupt, and control functions. RTC registers use the last 16 address locations of the SRAM. Internal double buffering of the clock and timer information registers prevents accessing transitional internal clock data during a read or write operation.
PAGE 8
CY14B256KA within the first 5 ms, the OSCF bit is set to ‘1’. The system must check for this condition and then write ‘0’ to clear the flag. Note that in addition to setting the OSCF flag bit, the time registers are reset to the ‘Base Time’, which is the value last written to the timekeeping registers. The control or calibration registers and the OSCEN bit are not affected by the ‘oscillator failed’ condition. The value of OSCF must be reset to ‘0’ when the time registers are written for the first time.
PAGE 9
CY14B256KA interrupt on INT pin is also generated on watchdog timeout. The flag and the hardware interrupt are both cleared when user reads the flags register. . Figure 3. Watchdog Timer Block Diagram Clock Divider Oscillator 32,768 KHz Interrupts are only generated while working on normal power and are not triggered when system is running in backup power mode. 1 Hz 32 Hz Counter Zero Compare internally fixed at approximately 200 ms. This mode is intended to reset a host microcontroller.
PAGE 10
CY14B256KA Figure 4. Interrupt Block Diagram WDF Watchdog Timer WIE P/L VCC PF Power Monitor Pin Driver PFE INT WDF - Watchdog Timer Flag WIE - Watchdog Interrupt Enable PF - Power Fail Flag PFE - Power Fail Enable AF - Alarm Flag AIE - Alarm Interrupt Enable P/L - Pulse Level H/L - High/Low VINT H/L VSS AF Clock Alarm AIE RTC External Components The RTC requires connecting an external 32.768 kHz crystal and C1, C2 load capacitance as shown in the Figure 5.
PAGE 11
CY14B256KA PCB Design Considerations for RTC RTC crystal oscillator is a low current circuit with high impedance nodes on their crystal pins. Due to lower timekeeping current of RTC, the crystal connections are very sensitive to noise on the board. Hence it is necessary to isolate the RTC circuit from other signals on the board. It is also critical to minimize the stray capacitance on the PCB. Stray capacitances add to the overall crystal load capacitance and therefore cause oscillation frequency errors.
PAGE 12
CY14B256KA Table 3.
PAGE 13
CY14B256KA Table 4. Register Map Detail Register Description CY14B256KA 0x7FFF Time Keeping - Years D7 D6 D5 D4 D3 D2 10s years D1 D0 Years Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years; upper nibble (four bits) contains the value for 10s of years. Each nibble operates from 0 to 9. The range for the register is 0–99.
PAGE 14
CY14B256KA Table 4. Register Map Detail (continued) Register Description CY14B256KA 0x7FF8 OSCEN Calibration/Control D7 D6 D5 OSCEN 0 Calibration sign D4 D3 D2 D1 D0 Calibration Oscillator Enable. When set to ‘1’, the oscillator is stopped. When set to ‘0’, the oscillator runs. Disabling the oscillator saves battery or capacitor power during storage. Calibration Sign Determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0) from the time-base.
PAGE 15
CY14B256KA Table 4. Register Map Detail (continued) Register Description CY14B256KA 0x7FF4 Alarm - Hours D7 D6 M 0 D5 D4 D3 10s alarm hours D2 D1 D0 Alarm hours Contains the alarm value for the hours and the mask bit to select or deselect the hours value. M 0x7FF3 Match. When this bit is set to ‘0’, the hours value is used in the alarm match. Setting this bit to ‘1’ causes the match circuit to ignore the hours value.
PAGE 16
CY14B256KA Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 C to +150 C Maximum accumulated storage time Transient voltage (< 20 ns) on any pin to ground potential ................. –2.0 V to VCC + 2.0 V Package power dissipation capability (TA = 25 °C) ................................................. 1.0 W Surface mount Pb soldering temperature (3 seconds) .................
PAGE 17
CY14B256KA DC Electrical Characteristics (continued) Over the Operating Range Parameter VCAP[12] VVCAP[13, 14] Description Storage capacitor Test Conditions Between VCAP pin and VSS Maximum voltage driven on VCAP VCC = Max pin by the device Min Typ [10] Max Unit 61 68 180 µF – – VCC V Data Retention and Endurance Over the Operating Range Parameter Description Min Unit 20 Years 1,000 K Max Unit Input capacitance (except HSB) TA = 25 C, f = 1 MHz, VCC = VCC(Typ) 7 pF Input capac
PAGE 18
CY14B256KA AC Test Loads Figure 7. AC Test Loads 577  577  3.0 V 3.0 V R1 R1 OUTPUT OUTPUT 30 pF R2 789  R2 789  5 pF AC Test Conditions Input pulse levels ...................................................0 V to 3 V Input rise and fall times (10%–90%) ............................ <3 ns Input and output timing reference levels ....................... 1.
PAGE 19
CY14B256KA AC Switching Characteristics Over the Operating Range Parameters [18] Cypress Alt Parameter Parameter 25 ns Description 45 ns Min Max Min Max Unit SRAM Read Cycle tACE tACS tRC Chip enable access time Read cycle time – 25 25 – – 45 45 – ns ns tAA [20] tAA Address access time – 25 – 45 ns tDOE tOE Output enable to data valid – 12 – 20 ns tOHA[20] tLZCE [21, 22] tHZCE [21, 22] tLZOE [21, 22] tHZOE [21, 22] tPU [21] tPD [21] tOH Output hold after address change 3
PAGE 20
CY14B256KA Switching Waveforms (continued) Figure 9. SRAM Read Cycle #2 (CE and OE Controlled) [25, 26] Address Address Valid tRC tHZCE tACE CE tAA tLZCE tHZOE tDOE OE tLZOE Data Output High Impedance Output Data Valid tPU ICC tPD Active Standby Figure 10. SRAM Write Cycle #1 (WE Controlled) [26, 27, 28] tWC Address Address Valid tSCE tHA CE tAW tPWE WE tSA tHD tSD Data Input Input Data Valid tLZWE tHZWE Data Output High Impedance Previous Data Figure 11.
PAGE 21
CY14B256KA AutoStore/Power-Up RECALL Over the Operating Range Parameter Min – Max 20 Unit ms STORE cycle duration – 8 ms tDELAY [31] Time allowed to complete SRAM write cycle – 25 ns VSWITCH Low voltage trigger level – 2.65 V tHRECALL tSTORE [29] [30] tVCCRISE [32] VHDIS[32] tLZHSB[32] tHHHD[32] Description Power-Up RECALL duration VCC rise time 150 – µs HSB output disable voltage – 1.
PAGE 22
CY14B256KA Software Controlled STORE/RECALL Cycle Over the Operating Range Parameter [35, 36] tRC tSA tCW tHA tRECALL tSS [37, 38] 25 ns Description Min 25 0 20 0 – – STORE/RECALL initiation cycle time Address setup time Clock pulse width Address hold time RECALL duration Soft sequence processing time 45 ns Max – – – – 200 100 Min 45 0 30 0 – – Max – – – – 200 100 Unit ns ns ns ns µs µs Switching Waveforms Figure 13.
PAGE 23
CY14B256KA Hardware STORE Cycle Over the Operating Range Parameter Description Min Max Unit tDHSB HSB to output active time when write latch not set – 25 ns tPHSB Hardware STORE pulse width 15 – ns Switching Waveforms Figure 15.
PAGE 24
CY14B256KA Truth Table For SRAM Operations HSB must remain HIGH for SRAM operations. Table 5.
PAGE 25
CY14B256KA Package Diagram Figure 17. 48-pin SSOP (300 Mils) Package Outline, 51-85061 51-85061 *F Document Number: 001-55720 Rev.
PAGE 26
CY14B256KA Acronyms Acronym Document Conventions Description Units of Measure BCD Binary Coded Decimal CE CMOS Chip Enable % percent Complementary Metal Oxide Semiconductor °C degree celsius EIA Electronic Industries Alliance F farad HSB I/O Hardware Store Busy Hz hertz Input/Output kHz kilohertz nvSRAM non-volatile Static Random Access Memory k kilohm OE Output Enable A microampere PCB RoHS Printed Circuit Board mA milliampere Restriction of Hazardous Substances F mi
PAGE 27
CY14B256KA Document History Page Document Title: CY14B256KA, 256-Kbit (32 K × 8) nvSRAM with Real Time Clock Document Number: 001-55720 Rev. ECN No. Orig. of Change Submission Date ** 2763469 GVCH 09/14/09 New data sheet. *A 2829117 GVCH 12/16/09 Added data retention and endurance table Updated STORE cycles to QuantumTrap from 200K to 1 Million Updated IBAK RTC backup current spec unit from nA to A Added Contents.
PAGE 28
CY14B256KA Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.