Specifications

CY8C21123/CY8C21223/CY8C21323
Document Number: 38-12022 Rev. *Y Page 8 of 46
Pin Information
This section describes, lists, and illustrates the CY8C21x23 PSoC device pins and pinout configurations. Every port pin (labeled with
a “P”) is capable of Digital I/O. However, V
SS
, V
DD
, SMP, and XRES are not capable of Digital I/O.
8-Pin Part Pinout
16-Pin Part Pinout
Table 2. Pin Definitions – CY8C21123 8-Pin SOIC
Pin
No.
Type
Pin
Name
Description
Figure 3. CY8C21123 8-Pin SOIC
Digital Analog
1 I/O I P0[5] Analog column mux input
2 I/O I P0[3] Analog column mux input
3 I/O P1[1] I
2
C serial clock (SCL), ISSP-SCLK
[3]
4 Power V
SS
Ground connection
5 I/O P1[0] I
2
C serial data (SDA), ISSP-SDATA
[3]
6 I/O I P0[2] Analog column mux input
7 I/O I P0[4] Analog column mux input
8 Power V
DD
Supply voltage
LEGEND: A = Analog, I = Input, and O = Output.
SOIC
1
2
3
4
8
7
6
5
V
DD
P0[4], A, I
P0[2], A, I
P1[0], I2C SDA
A, I, P0[5]
A, I, P0[3]
I2C SCL, P1[1]
V
SS
Table 3. Pin Definitions – CY8C21223 16-Pin SOIC
Pin
No.
Type
Pin
Name
Description
Figure 4. CY8C21223 16-Pin SOIC
Digital Analog
1 I/O I P0[7] Analog column mux input
2 I/O I P0[5] Analog column mux input
3 I/O I P0[3] Analog column mux input
4 I/O I P0[1] Analog column mux input
5 Power SMP SMP connection to required external
components
6 Power V
SS
Ground connection
7 I/O P1[1] I
2
C SCL, ISSP-SCLK
[3]
8 Power V
SS
Ground connection
9 I/O P1[0] I
2
C SDA, ISSP-SDATA
[3]
10 I/O P1[2]
11 I/O P1[4] Optional external clock input (EXTCLK)
12 I/O I P0[0] Analog column mux input
13 I/O I P0[2] Analog column mux input
14 I/O I P0[4] Analog column mux input
15 I/O I P0[6] Analog column mux input
16 Power V
DD
Supply voltage
LEGEND A = Analog, I = Input, and O = Output.
SOIC
V
DD
P0[6], A, I
P0[4], A, I
P0[2], A, I
P0[0], A, I
P1[4], EXTCLK
P1[2]
P1[0], I2C SDA
16
15
14
13
12
11
1
2
3
4
5
6
7
8
A, I, P0[7]
A, I, P0[5]
A, I, P0[3]
A, I, P0[1]
SMP
V
SS
I2C SCL, P1[1]
V
SS
10
9