Specifications

CY8C21123/CY8C21223/CY8C21323
Document Number: 38-12022 Rev. *Y Page 30 of 46
Figure 14. Definition for Timing for Fast/Standard Mode on the I
2
C Bus
Table 35. 2.7-V AC Characteristics of the I
2
C SDA and SCL Pins (Fast Mode Not Supported)
Symbol Description
Standard Mode Fast Mode
Units
Min Max Min Max
F
SCLI2C
SCL clock frequency 0 100 ––kHz
t
HDSTAI2C
Hold time (repeated) START Condition. After this period, the first clock
pulse is generated.
4.0 – – –µs
t
LOWI2C
Low period of the SCL clock 4.7 – – –µs
t
HIGHI2C
High period of the SCL clock 4.0 – – –µs
t
SUSTAI2C
Setup time for a repeated START condition 4.7 – – –µs
t
HDDATI2C
Data hold time 0 – – –µs
t
SUDATI2C
Data setup time 250 – – –ns
t
SUSTOI2C
Setup time for STOP condition 4.0 – – –µs
t
BUFI2C
Bus free time between a STOP and START condition 4.7 –––µs
t
SPI2C
Pulse width of spikes are suppressed by the input filter. – –––ns
I2C_SDA
I2C_SCL
S
Sr
SP
T
BUFI2C
T
SPI2C
T
SUSTOI2C
T
SUSTAI2C
T
LOWI2C
T
HIGHI2C
T
HDDATI2C
T
HDSTAI2C
T
SUDATI2C
START Condition Repeated START Condition
STOP Condition