Specifications

CY8C21123/CY8C21223/CY8C21323
Document Number: 38-12022 Rev. *Y Page 27 of 46
Table 29. 2.7-V AC Digital Block Specifications
Function Description Min Typ Max Units Notes
All
functions
Block input clock frequency – – 12.7 MHz 2.4 V < V
DD
< 3.0 V.
Timer Capture pulse width 100
[23]
– – ns
Input clock frequency, with or without capture – – 12.7 MHz
Counter Enable input pulse width 100 – – ns
Input clock frequency, no enable input – – 12.7 MHz
Input clock frequency, enable input – – 12.7 MHz
Dead band Kill pulse width:
Asynchronous restart mode 20 – – ns
Synchronous restart mode 100 – – ns
Disable mode 100 – – ns
Input clock frequency – – 12.7 MHz
CRCPRS
(PRS mode)
Input clock frequency – – 12.7 MHz
CRCPRS
(CRC mode)
Input clock frequency – – 12.7 MHz
SPIM Input clock frequency – – 6.35 MHz The SPI serial clock (SCLK)
frequency is equal to the input clock
frequency divided by 2.
SPIS Input clock (SCLK) frequency – – 4.1 MHz
Width of SS_ Negated between transmissions 100 – – ns
Transmitter Input clock frequency – – 12.7 MHz The baud rate is equal to the input
clock frequency divided by 8.
Receiver Input clock frequency – – 12.7 MHz The baud rate is equal to the input
clock frequency divided by 8.
Note
23. 100 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).