Specifications

CY8C24123A
CY8C24223A
CY8C24423A
Document Number: 38-12028 Rev. *V Page 57 of 71
Thermal Impedances Capacitance on Crystal Pins
Solder Reflow Specifications
Tab le 50 shows the solder reflow temperature limits that must not be exceeded.
Table 48. Thermal Impedances per Package
Package Typical 
JA
[38]
8-pin PDIP 123 °C/W
8-pin SOIC 185 °C/W
20-pin PDIP 109 °C/W
20-pin SSOP 117 °C/W
20-pin SOIC 81 °C/W
28-pin PDIP 69 °C/W
28-pin SSOP 101 °C/W
28-pin SOIC 74 °C/W
32-pin QFN
[39]
22 °C/W
Table 49. Typical Package Capacitance on Crystal Pins
Package Package Capacitance
8-pin PDIP 2.8 pF
8-pin SOIC 2.0 pF
20-pin PDIP 3.0 pF
20-pin SSOP 2.6 pF
20-pin SOIC 2.5 pF
28-pin PDIP 3.5 pF
28-pin SSOP 2.8 pF
28-pin SOIC 2.7 pF
32-pin QFN 2.0 pF
Table 50. Solder Reflow Specifications
Package
Maximum Peak
Temperature (T
C
)
Maximum Time
above T
C
– 5 °C
8-pin PDIP 260 °C 30 seconds
8-pin SOIC 260 °C 30 seconds
20-pin PDIP 260 °C 30 seconds
20-pin SSOP 260 °C 30 seconds
20-pin SOIC 260 °C 30 seconds
28-pin PDIP 260 °C 30 seconds
28-pin SSOP 260 °C 30 seconds
28-pin SOIC 260 °C 30 seconds
32-pin QFN 260 °C 30 seconds
Notes
38. T
J
= T
A
+ Power × 
JA
39. To achieve the thermal impedance specified for the QFN package, refer to Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages
available at www.amkor.com.