Datasheet

CY7C1526KV18
CY7C1513KV18
CY7C1515KV18
Document Number: 001-00435 Rev. *R Page 9 of 35
Functional Overview
The CY7C1526KV18, CY7C1513KV18, CY7C1515KV18 are
synchronous pipelined burst SRAMs with a read port and a write
port. The read port is dedicated to read operations and the write
port is dedicated to write operations. Data flows into the SRAM
through the write port and flows out through the read port. These
devices multiplex the address inputs to minimize the number of
address pins required. By having separate read and write ports,
the QDR II completely eliminates the need to turn around the
data bus and avoids any possible data contention, thereby
simplifying system design. Each access consists of four 9-bit
data transfers in the case of CY7C1526KV18, four 18-bit data
transfers in the case of CY7C1513KV18, and four 36-bit data
transfers in the case of CY7C1515KV18 in two clock cycles.
This device operates with a read latency of one and half cycles
when DOFF
pin is tied HIGH. When DOFF pin is set LOW or
connected to V
SS
then device behaves in QDR I mode with a
read latency of one clock cycle.
Accesses for both ports are initiated on the positive input clock
(K). All synchronous input timing is referenced from the rising
edge of the input clocks (K and K
) and all output timing is
referenced to the output clocks (C and C
, or K and K when in
single clock mode).
All synchronous data inputs (D
[x:0]
) pass through input registers
controlled by the input clocks (K and K
). All synchronous data
outputs (Q
[x:0]
) pass through output registers controlled by the
rising edge of the output clocks (C and C
, or K and K when in
single clock mode).
All synchronous control (RPS
, WPS, BWS
[x:0]
) inputs pass
through input registers controlled by the rising edge of the input
clocks (K and K
).
CY7C1513KV18 is described in the following sections. The
same basic descriptions apply to CY7C1526KV18 and
CY7C1515KV18.
Read Operations
The CY7C1513KV18 is organized internally as four arrays of 1M
x 18. Accesses are completed in a burst of four sequential 18-bit
data words. Read operations are initiated by asserting RPS
active at the rising edge of the positive input clock (K). The
address presented to the address inputs is stored in the read
address register. Following the next K clock rise, the
corresponding lowest order 18-bit word of data is driven onto the
Q
[17:0]
using C as the output timing reference. On the
subsequent rising edge of C, the next 18-bit data word is driven
onto the Q
[17:0]
. This process continues until all four 18-bit data
words are driven out onto Q
[17:0]
. The requested data is valid
0.45 ns from the rising edge of the output clock (C or C
, or K or
K
when in single clock mode). To maintain the internal logic, each
read access must be enabled to complete. Each read access
consists of four 18-bit data words and takes two clock cycles to
complete. Therefore, read accesses to the device cannot be
CQ
Echo Clock CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock for
output data (C
) of the QDR II. In the single clock mode, CQ is generated with respect to K. The timings
for the echo clocks are shown in the Switching Characteristics on page 26.
ZQ Input Output impedance matching input. This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ
, and Q
[x:0]
output impedance are set to 0.2 × RQ, where RQ is a resistor connected
between ZQ and ground. Alternatively, this pin can be connected directly to V
DDQ
, which enables the
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DOFF Input PLL turn off  Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timings
in the PLL turned off operation differs from those listed in this datasheet. For normal operation, this pin is
connected to a pull-up through a 10 k or less pull-up resistor. The device behaves in QDR I mode when
the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz with QDR
I timing.
TDO Output Test data out (TDO) pin for JTAG.
TCK Input Test clock (TCK) pin for JTAG.
TDI Input Test data in (TDI) pin for JTAG.
TMS Input Test mode select (TMS) pin for JTAG.
NC N/A Not connected to the die. Can be tied to any voltage level.
NC/144M N/A Not connected to the die. Can be tied to any voltage level.
NC/288M N/A Not connected to the die. Can be tied to any voltage level.
V
REF
Input-
Reference
Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
V
DD
Power Supply Power supply inputs to the core of the device.
V
SS
Ground Ground for the device.
V
DDQ
Power Supply Power supply inputs for the outputs of the device.
Pin Definitions (continued)
Pin Name I/O Pin Description