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EZ-USB FX2

Manual

Technical Reference

Summary of content (460 pages)

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EZ-USB FX2 Technical Reference Manual Cypress Semiconductor 3901 North First Street San Jose, CA 95134 Tel.: (800) 858-1810 (toll-free in the U.S.) (408) 943-2600 www.cypress.
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Cypress Disclaimer Agreement The information in this document is subject to change without notice and should not be construed as a commitment by Cypress Semiconductor Corporation Incorporated. While reasonable precautions have been taken, Cypress Semiconductor Corporation assumes no responsibility for any errors that may appear in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Cypress Semiconductor Corporation.
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Table of Contents Chapter 1. Introducing EZ-USB FX2 1.1 1.2 1.3 1.4 1.5 1.6 Introduction....................................................................................................................................1-1 An Introduction to USB..................................................................................................................1-1 The USB Specification ..................................................................................................................
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(Table of Contents) 2.3.3 Clear Feature .................................................................................................................2-11 2.3.4 Get Descriptor ...............................................................................................................2-12 2.3.4.1 Get Descriptor-Device........................................................................................2-14 2.3.4.2 Get Descriptor-Device Qualifier .......................................................
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(Table of Contents) 4.5 4.6 4.7 4.8 4.4.2.2 SOF Interrupt .....................................................................................................4-13 4.4.2.3 Suspend Interrupt...............................................................................................4-13 4.4.2.4 USB RESET Interrupt ........................................................................................4-13 4.4.2.5 HISPEED Interrupt ..........................................................................
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(Table of Contents) 7.4 7.5 7.6 7.7 7.3.2 EEPROM Load ................................................................................................................7-3 7.3.3 External ROM ..................................................................................................................7-3 CPU Reset Effects ........................................................................................................................7-4 USB Bus Reset ...............................................
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(Table of Contents) 9.2.4 FIFO Flag Pins (FLAGA, FLAGB, FLAGC, FLAGD)........................................................9-6 9.2.5 Control Pins (SLOE, SLRD, SLWR, PKTEND, FIFOADR[1:0]).......................................9-8 9.2.6 Slave FIFO Chip Select (SLCS) ....................................................................................9-10 9.2.7 Implementing Synchronous Slave FIFO Writes.............................................................9-10 9.2.
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(Table of Contents) 10.3.2.2.1 Non-Decision Point (NDP) States......................................................10-14 10.3.2.2.2 Decision Point (DP) States ................................................................10-16 10.3.3 Re-Executing a Task Within a DP State ....................................................................10-18 10.3.4 State Instructions.......................................................................................................10-21 10.3.4.
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(Table of Contents) Chapter 12. Instruction Set 12.1 Introduction................................................................................................................................12-1 12.1.1 Instruction Timing ........................................................................................................12-5 12.1.2 Stretch Memory Cycles (Wait States) ..........................................................................12-5 12.1.3 Dual Data Pointers................................
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(Table of Contents) 14.3.3 Mode 0.......................................................................................................................14-15 14.3.4 Mode 1.......................................................................................................................14-20 14.3.4.1 Mode 1 Baud Rate .........................................................................................14-20 14.3.4.2 Mode 1 Transmit ......................................................................
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(Table of Contents) 15.7.4 USB Interrupt Enable/Request ..................................................................................15-47 15.7.5 Endpoint Interrupt Enable/Request............................................................................15-49 15.7.6 GPIF Interrupt Enable/Request .................................................................................15-50 15.7.7 USB Error Interrupt Enable/Request .........................................................................
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(Table of Contents) 15.11.17 Endpoint 4 and 8 Slave FIFO Byte Count High .....................................................15-79 15.11.18 Endpoint 2, 4, 6, 8 Slave FIFO Byte Count Low....................................................15-79 15.11.19 Setup Data Pointer High and Low Address ...........................................................15-80 15.11.20 Setup Data Pointer Auto........................................................................................15-81 15.11.
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List of Figures Figure 1-1. Figure 1-2. Figure 1-3. Figure 1-4. Figure 1-5. Figure 1-6. Figure 1-7. Figure 1-8. Figure 1-9. Figure 1-10. Figure 1-11. Figure 1-12. Figure 1-13. Figure 1-14. Figure 1-15. Figure 1-16. Figure 1-17. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 3-1. Figure 3-2. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 4-6. Figure 4-7. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 6-1. USB Packets ...........................................
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(List of Figures) Figure 6-2. Figure 6-3. Figure 6-4. Figure 7-1. Figure 9-1. Figure 9-2. Figure 9-3. Figure 9-4. Figure 9-5. Figure 9-6. Figure 9-7. Figure 9-8. Figure 9-9. Figure 9-10. Figure 9-11. Figure 9-12. Figure 9-13. Figure 9-14. Figure 9-15. Figure 9-16. Figure 9-17. Figure 9-18. Figure 9-19. Figure 9-20. Figure 9-21. Figure 9-22. Figure 9-23. Figure 9-24. Figure 9-25. Figure 9-26. Figure 9-27. Figure 9-28. Figure 9-29. Figure 9-30. Figure 9-31. Figure 9-32. Figure 9-33. Figure 9-34. Figure 9-35.
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(List of Figures) Figure 9-37. Figure 9-38. Figure 9-39. Figure 9-40. Figure 9-41. Figure 9-42. Figure 9-43. Figure 9-44. Figure 9-45. Figure 9-46. Figure 10-1. Figure 10-2. Figure 10-3. Figure 10-4. Figure 10-5. Figure 10-6. Figure 10-7. Figure 10-8. Figure 10-9. Figure 10-10. Figure 10-11. Figure 10-12. Figure 10-13. Figure 10-14. Figure 10-15. Figure 10-16. Figure 10-17. Figure 10-18. Figure 10-19. Figure 10-20. Figure 10-21. Figure 10-22. Figure 10-23. Figure 10-24. Figure 10-25. Figure 10-26.
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(List of Figures) Figure 10-30. Figure 10-31. Figure 10-32. Figure 10-33. Figure 10-34. Figure 10-35. Figure 10-36. Figure 10-37. Figure 10-38. Figure 10-39. Figure 10-40. Figure 10-41. Figure 10-42. Figure 10-43. Figure 10-44. Figure 10-45. Figure 10-46. Figure 10-47. Figure 10-48. Figure 10-49. Figure 10-50. Figure 10-51. Figure 10-52. Figure 10-53. Figure 10-54. Figure 10-55. Figure 10-56. Figure 10-57. Figure 11-1. Figure 11-2. Figure 11-1. Figure 13-1. Figure 13-2. Figure 13-3. Figure 13-4.
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(List of Figures) Figure 14-2. Figure 14-3. Figure 14-4. Figure 14-5. Figure 14-6. Figure 14-7. Figure 14-8. Figure 14-9. Figure 14-10. Figure 14-11. Figure 14-12. Figure 14-13. Figure 14-14. Figure 14-15. Figure 14-16. Figure 15-1. Figure 15-2. Figure 15-3. Figure 15-4. Figure 15-5. Figure 15-6. Figure 15-7. Figure 15-8. Figure 15-9. Figure 15-10. Figure 15-11. Figure 15-12. Figure 15-13. Figure 15-14. Figure 15-15. Figure 15-16. Figure 15-17. Figure 15-18. Figure 15-19. Figure 15-20. Figure 15-21.
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(List of Figures) Figure 15-26. Figure 15-27. Figure 15-28. Figure 15-29. Figure 15-30. Figure 15-31. Figure 15-32. Figure 15-33. Figure 15-34. Figure 15-35. Figure 15-36. Figure 15-37. Figure 15-38. Figure 15-39. Figure 15-40. Figure 15-41. Figure 15-42. Figure 15-43. Figure 15-44. Figure 15-45. Figure 15-46. Figure 15-47. Figure 15-48. Figure 15-49. Figure 15-50. Figure 15-51. Figure 15-52. Figure 15-53. Figure 15-54. Figure 15-55. Figure 15-56. Figure 15-57. Figure 15-58. Figure 15-59. Figure 15-60.
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(List of Figures) Figure 15-66. Figure 15-67. Figure 15-68. Figure 15-69. Figure 15-70. Figure 15-71. Figure 15-72. Figure 15-73. Figure 15-74. Figure 15-75. Figure 15-76. Figure 15-77. Figure 15-78. Figure 15-79. Figure 15-80. Figure 15-81. Figure 15-82. Figure 15-83. Figure 15-84. Figure 15-85. Figure 15-86. Figure 15-87. Figure 15-88. Figure 15-89. Figure 15-90. Figure 15-91. Figure 15-92. Figure 15-93. Figure 15-94. Figure 15-95. Figure 15-96. Figure 15-97. Figure 15-98. Figure 15-99. Figure 15-100.
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(List of Figures) Figure 15-106. Figure 15-107. Figure 15-108. Figure 15-109. Figure 15-110. Figure 15-111. Figure 15-112. Figure 15-113. Figure 15-114. Figure 15-115. Figure 15-116. Figure 15-117. Figure 15-118. xx GPIF Data High (16-Bit Mode) .....................................................................................15-99 Read/Write GPIF Data LOW & Trigger Transaction ....................................................15-99 Read GPIF Data LOW, No Transaction Trigger ..........................
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List of Tables Table 1-1. Table 1-2. Table 1-3. Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. Table 2-8. Table 2-9. Table 2-10. Table 2-11. Table 2-12. Table 2-13. Table 2-14. Table 2-15. Table 2-16. Table 2-17. Table 2-18. Table 2-19. Table 2-20. Table 2-21. Table 2-22. Table 2-23. Table 2-24. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 3-8. Table 4-1. USB PIDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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(List of Tables) Table 4-2. Table 4-3. Table 4-4. Table 4-5. Table 4-6. Table 4-7. Table 4-8. Table 4-9. Table 4-10. Table 4-11. Table 4-12. Table 4-13. Table 4-14. Table 4-15. Table 4-16. Table 7-1. Table 8-1. Table 8-2. Table 8-3. Table 8-4. Table 8-5. Table 8-6. Table 8-7. Table 8-8. Table 8-9. Table 9-1. Table 9-2. Table 9-3. Table 10-1. Table 10-2. Table 10-3. Table 10-4. Table 10-5. Table 10-6. Table 10-7. Table 10-8. Table 11-1. Table 11-2. Table 11-3. Table 11-4. xxiv IE Register — SFR 0xA8 . . .
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(List of Tables) Table 11-5. Table 12-1. Table 12-2. Table 12-3. Table 12-4. Table 13-1. Table 13-2. Table 13-3. Table 13-4. Table 13-5. Table 13-6. Table 13-7. Table 13-8. Table 13-9. Table 13-10. Table 13-11. Table 13-12. Table 14-1. Table 14-2. Table 14-3. Table 14-4. Table 14-5. Table 14-6. Table 14-7. Table 14-8. Table 14-9. Table 14-10. Table 14-11. Table 14-12. Table 14-13. Table 14-14. Table 14-15. Table 14-16. Table 15-1. Table 15-2. Table 15-3. Table 15-4. Table 15-5. Table 15-6. Table 15-7.
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(List of Tables) Table 15-8. Table 15-9. Table 15-10. Table 15-11. Table 15-12. Table 15-13. Table 15-14. Table 15-15. Table 15-16. Table 15-17. Table 15-18. Table 15-19. Table 15-20. IFCFG Selection of Port I/O Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17 FIFO Flag Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-19 FIFOADR1 FIFOADR0 Pin Correspondence . . . . . . . . . . . . . . . . . . . . . . . . . .
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(List of Tables) Table A-24 Table A-25 Endpoint Descriptor (EP6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Endpoint Descriptor (EP8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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xxviii List of Tables
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Chapter 1 1.1 Introducing EZ-USB FX2 Introduction The Universal Serial Bus (USB) has gained wide acceptance as the connection method of choice for low and medium speed PC peripherals. Equally successful in the Windows and Macintosh worlds, USB has delivered on its promises of easy attachment, an end to configuration hassles, and true plug-and-play operation. The second generation of the USB specification, “USB 2.
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EZ-USB FX2 Technical Reference Manual matically loads the device’s driver into the operating system. When the device is unplugged, the operating system automatically logs it off and unloads its driver. • USB devices do not use DIP switches, jumpers, or configuration programs. There is never an IRQ, DMA, memory, or I/O conflict with a USB device. • USB expansion hubs make the bus simultaneously available to dozens of devices.
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1.4 Host Is Master This is a fundamental USB concept. There is exactly one master in a USB system: the host computer. USB devices respond to host requests. USB devices cannot send information among themselves, as they could if USB were a peer-to-peer topology. However, there is one case where a USB device can initiate signaling without prompting from the host. After being put into a low-power “suspend” mode by the host, a device can signal a “remote wakeup”.
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EZ-USB FX2 Technical Reference Manual O U T A D D R E N D P C R C 5 D A T A 1 Payload D ata Token P acket D ata P acket 1 2 C R C 1 6 A C K H /S P kt 3 O U T A D D R E N D P C R C 5 Token P acket 4 D A T A 0 Payload D ata D ata P acket 5 C R C 1 6 A C K H /S P kt 6 Figure 1-1. USB Packets Figure 1-1 illustrates a USB OUT transfer. Host traffic is shown in solid shading, while device traffic is shown crosshatched. Packet 1 is an OUT token, indicated by the OUT PID.
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• STALL means that something unforeseen went wrong (probably as a result of miscommunication or lack of cooperation between the host and device software). A device sends the STALL handshake to indicate that it doesn’t understand a device request, that something went wrong on the peripheral end, or that the host tried to access a resource that wasn’t there. It’s like HALT, but better, because USB provides a way to recover from a stall.
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EZ-USB FX2 Technical Reference Manual 1.8 USB Transfer Types USB defines four transfer types. These match the requirements of different data types delivered over the bus. 1.8.1 Bulk Transfers I N A D D R E N D P C R C 5 Token Packet D A T A 1 C R C 1 6 Payload Data Data Packet A O D U D T R A C K E N D P D A T A 0 C R C 5 Token Packet H/S Pkt Payload Data Data Packet C R C 1 6 A C K H/S Pkt Figure 1-2.
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1.8.3 Isochronous Transfers A D D R I N E N D P D A T A 0 C R C 5 C R C 1 6 Payload Data Token Packet Data Packet Figure 1-4. An Isochronous Transfer Isochronous data is time-critical and used to stream data like audio and video. An isochronous packet may contain up to 1023 bytes at full speed, or up to 1024 bytes at high speed. Time of delivery is the most important requirement for isochronous data. In every USB frame, a certain amount of USB bandwidth is allocated to isochronous transfers.
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EZ-USB FX2 Technical Reference Manual Control transfers configure and send commands to a device. Because they’re so important, they employ the most extensive USB error checking. The host reserves a portion of each USB frame for Control transfers. Control transfers consist of two or three stages. The SETUP stage contains eight bytes of USB CONTROL data. An optional DATA stage contains more data, if required.
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1.10 The Serial Interface Engine (SIE) O U T A D D R E N D P C R C 5 Token Packet D A T A 1 Payload Data Data Packet C R C 1 6 A C K H/S Pkt O U T A D D R E N D P C R C 5 D A T A 0 Token Packet Payload Data Data Packet C R C 1 6 A C K H/S Pkt Payload Data Serial Interface Engine (SIE) D+ D- USB Transceiver Payload Data A C K Figure 1-6.
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EZ-USB FX2 Technical Reference Manual RAM which can be loaded over the USB. This makes modifications, specification revisions, and updates a snap. The FX2’s “smart” SIE performs much more than the basic functions shown in Figur e1-6; it can perform a full enumeration by itself, which allows the FX2 to connect as a USB device and download code into its RAM while its CPU is held in reset.
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1.12 EZ-USB FX2 Architecture D+ D- Serial Interface Engine (SIE) USB Connector OUT data IN data USB Interface USB Transceiver CPU (Enhanced 8051) Slave FIFOs I/O Ports GPIF 16 EZ-USB FX2 Program & Data RAM CTL RDY Figure 1-7. FX2 56-pin Package Simplified Block Diagram The FX2 packs all the intelligence required by a USB peripheral interface into a compact integrated circuit. As Figure 1-7 illustrates, an integrated USB transceiver connects to the USB bus pins D+ and D-.
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EZ-USB FX2 Technical Reference Manual The FIFOs can be controlled by an external master, which either supplies a clock and clockenable signals to operates synchronously, or strobe signals to operate asynchronously. Alternately, the FIFOs can be controlled by an internal FX2 timing generator called the General Programmable Interface (GPIF). The GPIF serves as an internal master, interfacing directly to the FIFOs and generating user-programmed control signals for the interface to external logic.
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1.13 FX2 Feature Summary FX2 includes the following features: • On-chip 480 Mbits/sec transceiver, PLL and SIE—the entire USB 2.0 physical layer (PHY). • Double-, triple- and quad-buffered endpoint FIFOs accommodate the 480 MBits/sec USB 2.0 data rate. • Built-in, enhanced 8051 running at up to 48 MHz. - Fully featured: 256 bytes of register RAM, two USARTs, three timers, two data pointers. - Fast: four clocks (83.3 nanoseconds at 48 MHz) per instruction cycle.
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EZ-USB FX2 Technical Reference Manual the firmware associated with the USB protocol is simplified, leaving code space and bandwidth available for the CPU’s primary duty—to help implement your device. On the device side, abundant input/output resources are available, including I/O ports, USARTs, and an I² C -compatible bus master controller. These resources are described in Chapter 13, "Input/Output", and Chapter 14, "Timers/Counters and Serial Interface".
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1.15 FX2 Block Diagram D- S IO S IO 2 i2c com patible 2 port A 8 8 1 PLL 80 51 48 M H z 4 KB Endpoint R AM U SB regs 0.5K D ata R AM port B 8 KB Pgm /D ata R AM E xt C lock 2 port E 24 M H z crystal PH Y Interface port C U SB 2.0 PH Y D ata(8) Addr(16) D+ port D F IF O S G P IF 14 7 16 16 4 G eneral P urpose Interface (e.g. AT A, EPP , etc.) Figure 1-9. FX2 Block Diagram Chapter 1.
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EZ-USB FX2 Technical Reference Manual 1.16 Packages FX2 is available in three packages: 56 SSOP 8 x1 8 x2 .3 mm 128 TQFP 1 4 x2 0 x1.4 mm 100 TQFP 1 4 x2 0 x1.4 mm Figure 1-10. 56-pin, 100-pin, and 128-pin FX2 Packages 1.16.1 56-Pin Package Twenty-four general-purpose I/O pins (ports A, B, and D) are available.
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1.16.2 100-Pin Package The 100-pin package adds functionality to the 56-pin package: • Two additional 8-bit I/O ports: PORTC and PORTE • Seven additional GPIF Control (CTL) and Ready (RDY) signals • Nine non-multiplexed peripheral signals (two USARTs, three timer inputs, INT4, and INT5) • Eight additional control signals multiplexed onto PORTE • Nine GPIF address lines, multiplexed onto PORTC (eight) and PORTE (one) • RD and WR signals which may be used as read and write strobes for PORTC 1.16.
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EZ-USB FX2 Technical Reference Manual In the “Slave FIFO” mode, external logic or an external processor interfaces directly to the FX2 endpoint FIFOs. In this mode, the GPIF is not active, since external logic has direct FIFO control. Therefore, the basic FIFO signals (flags, selectors, strobes) are brought out on FX2 pins. The external master can be asynchronous or synchronous, and it may supply its own independent clock to the FX2 interface.
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Ports XTALIN XTALOUT DPLUS DMINUS SCL SDA 56 GPIF Master PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 RESET# WAKEUP IFCLK CLKOUT INT0#/PA0 INT1#/PA1 PA2 WU2/PA3 PA4 PA5 PA6 PA7 100 PE7/GPIFADR8 PE6/T2EX PE5/INT6 PE4/RxD1OUT PE3/RxD0OUT PE2/T2OUT PE1/T1OUT PE0/T0OUT A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 FD[15] FD[14] FD[13] FD[12] FD[11] FD[10] FD[9] FD[8] FD[7] FD[6] FD[5] FD[4] FD[3] FD[2] FD[1] FD[0] Slave FIFO ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ FD[15] FD[14] FD[1
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EZ-USB FX2 Technical Reference Manual 1.
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21 22 23 24 25 26 27 28 29 30 81 20 82 19 83 18 84 17 85 16 86 15 87 14 88 13 89 12 90 11 91 10 92 9 93 8 94 7 95 6 96 5 97 4 98 3 PD1/FD9 PD2/FD10 PD3/FD11 INT5 VCC PE0/T0OUT PE1/T1OUT PE2/T2OUT PE3/RXD0OUT PE4/RXD1OUT PE5/INT6 PE6/T2EX PE7/GPIFADR8 GND PD4/FD12 PD5/FD13 PD6/FD14 PD7/FD15 GND CLKOUT 2 99 100 1 VCC GND RDY0/*SLRD RDY1/*SLWR RDY2 RDY3 RDY4 RDY5 AVCC XTALOUT XTALIN AGND NC NC NC VCC DPLUS DMINUS GND VCC GND INT4 T0 T1 T2 IFCLK RESERVED BKPT SCL SDA P
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EZ-USB FX2 Technical Reference Manual 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PD5/FD13 PD4/FD12 PD6/FD14 PD3/FD11 PD7/FD15 PD2/FD10 GND PD1/FD9 CLKOUT PD0/FD8 VCC *WAKEUP GND VCC RDY0/*SLRD RESET GND RDY1/*SLWR PA7/*FLAGD/SLCS AVCC XTALOUT PA6/PKTEND XTALIN PA5/FIFOADR1 AGND PA4/FIFOADR0 VCC PA3/*WU2 DPLUS PA2/*SLOE DMINUS PA1/INT1 GND PA0/INT0 VCC VCC CTL2/*FLAGC GND CTL1/*FLAGB IFCLK CTL0/*FLAGA RESERVED GND SCL CY7C68013 SDA 56-pin SSOP VCC GND VCC PB7/FD7 PB0/FD0 PB6
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1.18 FX2 Endpoint Buffers The USB Specification defines an endpoint as a source or sink of data. Since USB is a serial bus, a device endpoint is actually a FIFO which sequentially empties or fills with USB data bytes. The host selects a device endpoint by sending a 4-bit address and a direction bit. Therefore, USB can uniquely address 32 endpoints, IN0 through IN15 and OUT0 through OUT15. From the FX2’s point of view, an endpoint is a buffer full of bytes received or held for transmission over the bus.
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EZ-USB FX2 Technical Reference Manual The eight SETUP bytes in a CONTROL transfer do not appear in the 64-byte EP0 endpoint buffer. Instead, to simplify programming, the FX2 automatically stores the eight SETUP bytes in a separate buffer (SETUPDAT, at 0xE6B8-0xE6BF). EP1IN and EP1OUT use separate 64 byte buffers. FX2 firmware can configure these endpoints as BULK, INTERRUPT or ISOCHRONOUS. These endpoints, as well as EP0, are accessible only by FX2 firmware.
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1.19 External FIFO Interface The large data FIFOs (endpoints 2, 4, 6 and 8) in the FX2 are designed to move high speed (480 Mbits/sec) USB data on and off chip without introducing any bandwidth bottlenecks. They accomplish this goal by implementing the following features: 1. Direct interface with outside logic, with the FX2’s CPU out of the data path. 2. “Quantum FIFO” architecture instantaneously moves (“commits”) packets between the USB and the FIFOs. 3.
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EZ-USB FX2 Technical Reference Manual EP8 EP6 EP4 EP2 FD [15:0] D ata PKT EN D (IN FU LL) (O U T EM PT Y) FIFO S LR D S LW R P K TE N D Asynchronous (PR G FLAG ) IFC LK SLR D IFC LK SLW R select SLO E S LR D S LW R P K TE N D Synchronous FIFO AD R 1 FIFO AD R 0 Figure 1-16. FX2 FIFOs in “Slave FIFO” Mode Figure 1-16 illustrates the outside-world view of the FX2 data FIFOs configured as “Slave FIFOs”.
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EP8 EP6 EP4 EP2 D ata FD [15:0] FLAG S F IF O SLR D SLW R SLO E SLR D 6 select 6 G P IF 9 CTL RDY G PIFAD R 8051 R D Y 8051 IN T IFC LK 30 M H z 48 M H z IFC LK Figure 1-17. FX2 FIFOs in “GPIF Master” Mode External systems that connect to the FX2 FIFOs must provide control circuitry to select FIFOs, check flags, clock data, etc. FX2 contains a sophisticated control unit (the General Programmable Interface, or GPIF) which can replace this external logic.
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EZ-USB FX2 Technical Reference Manual menting “wait states”. GPIFADR pins present a 9-bit address to the interface that may be incremented as data is transferred. The 8051 INT signal is a ‘hook’ that can signal the FX2’s CPU in the middle of a transaction; GPIF operation resumes once the CPU asserts its own 8051 RDY signal. This ‘hook’ permits great flexibility in the generation of GPIF waveforms. 1.
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Chapter 2 2.1 Endpoint Zero Introduction Endpoint zero has special significance in a USB system. It is a CONTROL endpoint, and it is required by every USB device. The USB host uses special SETUP tokens to signal transfers that deal with device control; only CONTROL endpoints accept these special tokens. The USB host sends a suite of standard device requests over endpoint zero. These standard requests are fully defined in Chapter 9 of the USB Specification.
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EZ-USB FX2 Technical Reference Manual 2.
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The STATUS stage consists of an empty data packet with the opposite direction of the data stage, or an IN if there was no data stage. This empty data packet gives the device a chance to ACK or NAK the entire CONTROL transfer. The HSNAK bit holds off the completion of a CONTROL transfer until the device has had time to respond to a request.
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EZ-USB FX2 Technical Reference Manual must always be accepted and never NAK’d. It is possible, therefore, that a CONTROL transfer could arrive while the firmware is still servicing a previous one. In this case, the earlier CONTROL transfer service should be aborted and the new one serviced. The SUTOK interrupt gives advance warning that a new CONTROL transfer is about to overwrite the eight SETUPDAT bytes.
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2.3 USB Requests The Universal Serial Bus Specification Version 2.0, Chapter 9, "USB Device Framework" defines a set of Standard Device Requests. When the firmware is in control of endpoint zero (RENUM=1), the FX2 handles only one of these requests (Set Address) automatically; it relies on the firmware to support all of the others. The firmware acts on device requests by decoding the eight bytes contained in the SETUP packet and available at SETUPDAT. Table2-1 defines these eight bytes. Table 2-1.
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EZ-USB FX2 Technical Reference Manual . Table 2-2.
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2.3.1 Get Status The USB Specification defines three USB status requests. A fourth request, to an interface, is declared in the spec as “reserved.” The four status requests are: • Remote Wakeup (Device request) • Self-Powered (Device request) • Stall (Endpoint request) • Interface request (reserved) The FX2 automatically asserts the SUDAV interrupt to tell the firmware to decode the SETUP packet and supply the appropriate status information.
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EZ-USB FX2 Technical Reference Manual As Figure 2-4 illustrates, the firmware responds to the SUDAV interrupt by decoding the eight bytes the FX2 has copied into RAM at SETUPDAT. The firmware answers a Get Status request (bRequest=0) by loading two bytes into the EP0BUF buffer and loading the byte count register EP0BCH:L with the value 0x0002. The FX2 then transmits these two bytes in response to an IN token.
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Endpoint zero is a CONTROL endpoint, which by USB definition is bi-directional. Therefore, it has only one stall bit. About STALL The USB STALL handshake indicates that something unexpected has happened. For instance, if the host requests an invalid alternate setting or attempts to send data to a nonexistent endpoint, the device responds with a STALL handshake over endpoint zero instead of ACK or NAK. Stalls are defined for all endpoint types except ISOCHRONOUS, which does not employ handshakes.
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EZ-USB FX2 Technical Reference Manual 2.3.2 Set Feature Set Feature is used to enable remote wakeup or stall an endpoint. No data stage is required. Table 2-6.
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3. Restore the stalled endpoint to its default condition, ready to send or accept data after the stall condition is removed by the host (via a Clear Feature/Stall request). For EP1 IN, for example, firmware should clear the BUSY bit in the EP1CS register; for EP1OUT, firmware should load any value into the EP1 byte-count register. 4. Clear the HSNAK bit in the EP0CS register (by writing 1 to it) to terminate the Set Feature/Stall CONTROL transfer.
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EZ-USB FX2 Technical Reference Manual Table 2-9. Clear Feature-Endpoint (Clear Stall) Byte Field Value Meaning Firmware Response 0 bmRequestType 0x02 OUT, Endpoint Clear the STALL bit for the 1 bRequest 0x01 “Clear Feature” indicated endpoint.
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SETUP Stage S A E C E D N R T D D C U R P 5 P Token Packet D A T A 0 8 bytes Setup Data Data Packet C R C 1 6 A C K SETUPDAT 8 RAM bytes H/S Pkt SUDAV Interrupt DATA Stage I N A D D R E N D P C R C 5 D A T A 1 Payload Data Data Packet Token Packet C R C 1 6 A C K H/S Pkt I N A D D R E N D P C R C 5 Token Packet D A T A 0 Payload Data Data Packet EP0IN Interrupt STATUS Stage O U T A D D R E N D P C R C 5 Token Packet D A T A 1 Data C R C 1 6 Pkt C R C 1 6 A C K H/S Pkt EP0IN
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EZ-USB FX2 Technical Reference Manual 2.3.4.1 Get Descriptor-Device Table 2-10. Get Descriptor-Device Byte Field Value Meaning Firmware Response 0 bmRequestType 0x80 IN, Device Set SUDPTR H:L to start of 1 bRequest 0x06 “Get Descriptor” Device Descriptor table in RAM.
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Data Pointer. However, this would waste bandwidth because it requires byte transfers into the EP0BUF Buffer; using the Setup Data Pointer doesn’t. 2.3.4.2 Get Descriptor-Device Qualifier Table 2-11.
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EZ-USB FX2 Technical Reference Manual 2.3.4.4 Get Descriptor-String Table 2-13. Get Descriptor-String Byte Field Value Meaning Firmware Response 0 bmRequestType 0x80 IN, Device Set SUDPTR H:L to start of 1 bRequest 0x06 “Get_Descriptor” String Descriptor table in 2 wValueL STR String Number RAM.
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2.3.5 Set Descriptor Table 2-15. Set Descriptor-Device Byte Field Value Meaning Firmware Response 0 bmRequestType 0x00 OUT, Device Read device descriptor data over 1 bRequest 0x07 “Set_Descriptor” EP0BUF. 2 wValueL 0x00 3 wValueH 0x01 4 wIndexL 0x00 5 wIndexH 0x00 6 wLengthL LenL 7 wLengthH LenH Descriptor Type: Device Table 2-16.
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EZ-USB FX2 Technical Reference Manual Table 2-17. Set Descriptor-String Byte Field Value Meaning Firmware Response 0 bmRequestType 0x00 IN, Device Read string descriptor data over 1 bRequest 0x07 “Get_Descriptor” EP0BUF.
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Configurations, Interfaces, and Alternate Settings A USB device has one or more configurations. Only one configuration is active at any time. A configuration has one or more interfaces, all of which are concurrently active. Multiple interfaces allow different host-side device drivers to be associated with different portions of a USB device. Each interface has one or more alternate settings. Each alternate setting has a collection of one or more endpoints.
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EZ-USB FX2 Technical Reference Manual 2.3.5.1 Set Configuration Table 2-18. Set Configuration Byte Field Value Meaning Firmware Response 0 bmRequestType 0x00 OUT, Device Read and store CFG, change 1 bRequest 0x09 “Set Configuration” configurations in firmware.
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2.3.7 Set Interface This confusingly-named USB command actually sets alternate settings for a specified interface. USB devices can have multiple concurrent interfaces. For example, a device may have an audio system that supports different sample rates, and a graphic control panel that supports different languages. Each interface has a collection of endpoints. Except for endpoint 0, which each interface uses for device control, endpoints may not be shared between interfaces.
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EZ-USB FX2 Technical Reference Manual 2.3.8 Get Interface Table 2-21. Get Interface (Actually, Get Alternate Setting #AS for interface #IF) Byte Field Value Meaning Firmware Response 0 bmRequestType 0x81 IN, Device Send AS for Interface #IF over 1 bRequest 0x0A “Get Interface” EP0.
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2.3.10 Sync Frame Table 2-22. Sync Frame Byte Field Value Meaning Firmware Response 0 bmRequestType 0x82 IN, Endpoint Send a frame number over EP0 1 bRequest 0x0C “Sync Frame” to synchronize endpoint #EP 2 wValueL 0x00 3 wValueH 0x00 4 wIndexL EP 5 wIndexH 0x00 6 wLengthL 2 LenL 7 wLengthH 0 LenH Endpoint number The Sync Frame request is used to establish a marker in time so the host and USB device can synchronize multi-frame transfers over isochronous endpoints.
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EZ-USB FX2 Technical Reference Manual 2.3.11 Firmware Load The USB endpoint-zero protocol provides a mechanism for mixing vendor-specific requests with standard device requests. Bits 6:5 of the bmRequestType field are set to 00 for a standard device request and to 10 for a vendor request. Table 2-23.
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Chapter 3 3.1 Enumeration and ReNumeration™ Introduction The FX2’s configuration is soft: Code and data are stored in internal RAM, which can be loaded from the host over the USB interface. FX2-based USB peripherals can operate without ROM, EPROM, or FLASH memory, shortening production lead times and making firmware updates extremely simple. To support this soft configuration, the FX2 is capable of enumerating as a USB device without firmware.
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EZ-USB FX2 Technical Reference Manual 1. If no off-chip memory (either on the I²C-compatible bus or on the address/data bus) is connected to the FX2, it enumerates as the Default USB Device, with descriptors and VID / PID / DID supplied by hardwired internal logic (Table 3-3). RENUM is set to 0, indicating that the Default USB Device automatically handles device requests. 2.
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3.3 The Default USB Device The Default USB Device consists of a single USB configuration containing one interface (interface 0) and alternate settings 0, 1, 2 and 3. The endpoints and MaxPacketSizes reported for this device are shown in Table 3-1 (full speed) and Table 3-2 (high speed). Note that alternate setting zero consumes no interrupt or isochronous bandwidth, as recommended by the USB Specification. Table 3-1.
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EZ-USB FX2 Technical Reference Manual 3.4 EEPROM Boot-load Data Formats This section describes three EEPROM boot-load scenarios and the EEPROM data formats that support them. The three scenarios are: • No EEPROM, or EEPROM with invalid boot data • “C0” EEPROM (load custom VID / PID / DID only) • “C2” EEPROM (load firmware to on-chip RAM) 3.4.
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3.4.2 Serial EEPROM Present, First Byte is 0xC0 Table 3-4.
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EZ-USB FX2 Technical Reference Manual 3.4.3 Serial EEPROM Present, First Byte is 0xC2 If, at power-on reset, the FX2 detects an EEPROM connected to its I² C -compatible with the value 0xC2 at address 0, the FX2 loads the EEPROM data into RAM. It also sets the RENUM bit to 1, causing device requests to be handled by the firmware instead of the Default USB Device. The “C2 Load” EEPROM data format is shown in Table3-5. Table 3-5.
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Bytes 1-6 of a C2 EEPROM can be loaded with VID / PID / DID bytes if it is desired at some point to run the firmware with RENUM = 0 (i.e., FX2 logic handles device requests), using the EEPROM VID / PID / DID rather than the development-only VID / PID / DID values shown in Table 3-3. One or more data records follow, starting at EEPROM address 8.
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EZ-USB FX2 Technical Reference Manual 3.5 EEPROM Configuration Byte The configuration byte is valid for both EEPROM load formats (C0 and C2) and has the following format: Configuration b7 b6 b5 b4 b3 b2 b1 b0 0 DISCON 0 0 0 0 0 400KHz Figure 3-1. EEPROM Configuration Byte Bit 6: DISCON USB Disconnect A USB hub or host detects attachment of a full-speed device by sensing a high level on the D+ wire. A USB device provides this high level using a 1500-ohm resistor between D+ and 3.
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3.6 The RENUM Bit An FX2 control bit called “RENUM” (ReNumerated) determines whether USB device requests over endpoint zero are handled by the Default USB Device or by FX2 firmware. At power-on reset, the RENUM bit (USBCS.1) is zero, indicating that the Default USB Device will automatically handle USB device requests. Once firmware has been downloaded to the FX2 and the CPU is running, it can set RENUM=1 so that subsequent device requests will be handled by the downloaded firmware and descriptor tables.
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EZ-USB FX2 Technical Reference Manual 3.7 FX2 Response to Device Requests (RENUM=0) Table 3-6 shows how the Default USB Device responds to endpoint zero device requests when RENUM=0. Table 3-6.
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3.8 FX2 Vendor Request for Firmware Load Prior to ReNumeration, the host downloads data into the FX2’s internal RAM. The host can access two on-chip FX2 RAM spaces — Program / Data RAM at 0x0000-0x1FFF and Data RAM at 0xE000-0xE1FF — which it can download or upload whether the CPU is in reset or running: These two RAM spaces may also be boot-loaded by a “C2” EEPROM connected to the I²C-compatible bus. The host may also write to the CPUCS register to put the CPU in or out of reset.
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EZ-USB FX2 Technical Reference Manual These upload and download requests are always handled by the FX2, regardless of the state of the RENUM bit. The bRequest value 0xA0 is reserved for this purpose. It should never be used for another vendor request. Cypress Semiconductor also reserves bRequest values 0xA1 through 0xAF; devices should not use these bRequest values.
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Chapter 4 Interrupts 4.1 Introduction The EZ-USB FX2’s interrupt architecture is an enhanced and expanded version of the standard 8051’s. The FX2 responds to the interrupts shown in Table 4-1; interrupt sources that are not present in the standard 8051 are shown in bold type. . Table 4-1.
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EZ-USB FX2 Technical Reference Manual 4.2 SFRs The following SFRs are associated with interrupt control: • IE - SFR 0xA8 (Table 4-2) • IP - SFR 0xB8 (Table 4-3) • EXIF - SFR 0x91 (Table 4-4) • EICON - SFR 0xD8 (Table 4-5) • EIE - SFR 0xE8 (Table 4-6) • EIP - SFR 0xF8 (Table 4-7) The IE and IP SFRs provide interrupt enable and priority control for the standard interrupt unit, as with the standard 8051. Additionally, these SFRs provide control bits for the Serial Port 1 interrupt.
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Table 4-3. IP Register — SFR 0xB8 Bit Function IP.7 Reserved. Read as 1. IP.6 PS1 - Serial Port 1 interrupt priority control. PS1 = 0 sets Serial Port 1 interrupt (TI_1 or RI_1) to low priority. PS1 = 1 sets Serial port 1 interrupt to high priority. IP.5 PT2 - Timer 2 interrupt priority control. PT2 = 0 sets Timer 2 interrupt (TF2) to low priority. PT2 = 1 sets Timer 2 interrupt to high priority. IP.4 PS0 - Serial Port 0 interrupt priority control.
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EZ-USB FX2 Technical Reference Manual Table 4-5. EICON Register — SFR 0xD8 Bit Function EICON.7 SMOD1 - Serial Port 1 baud rate doubler enable. When SMOD1 = 1, the baud rate for Serial Port 1 is doubled. EICON.6 Reserved. Read as 1. EICON.5 ERESI - Enable Resume interrupt. ERESI = 0 disables the Resume interrupt. ERESI = 1 enables interrupts generated by the resume event. EICON.4 RESI - Wakeup interrupt flag.
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Table 4-7. EIP Register — SFR 0xF8 Bit EIP.7-5 Function Reserved. Read as 1. EIP.4 PX6 - External interrupt 6 priority control. PX6 = 0 sets external interrupt 6 (INT6) to low priority. PX6 = 1 sets external interrupt 6 to high priority. EIP.3 PX5 - External interrupt 5 priority control. PX5 = 0 sets external interrupt 5 (INT5) to low priority. PX5=1 sets external interrupt 5 to high priority. EIP.2 PX4 - External interrupt 4 priority control.
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EZ-USB FX2 Technical Reference Manual 4.3 Interrupt Processing When an enabled interrupt occurs, the FX2 completes the instruction it’s currently executing, then vectors to the address of the interrupt service routine (ISR) associated with that interrupt (see Table 4-9). The FX2 executes the ISR to completion unless another interrupt of higher priority occurs. Each ISR ends with a RETI (return from interrupt) instruction.
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Table 4-9. Interrupt Flags, Enables, Priority Control, and Vectors Interrupt Description Interrupt Request Flag Interrupt Enable Assigned Natural Interrupt Priority Priority Vector Control RESUME Resume interrupt EICON.4 EICON.5 Always Highest INT0 External interrupt 0 TCON.1 IE.0 TF0 Timer 0 interrupt TCON.5 IE.1 INT1 External interrupt 1 TCON.3 IE.2 TF1 Timer 1 interrupt TCON.7 IE.3 TI_0 or RI_0 Serial port 0 transmit or receive interrupt SCON0.1 (TI.0) SCON0.
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EZ-USB FX2 Technical Reference Manual 4.3.2 Interrupt Sampling The internal timers and serial ports generate interrupts by setting the interrupt flag bits shown in Table 4-9. These interrupts are sampled once per instruction cycle (i.e., once every 4 CLKOUT cycles). INT0 and INT1 are both active low and can be programmed to be either edge-sensitive or levelsensitive, through the IT0 and IT1 bits in the TCON SFR.
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4.4.2 USB Interrupts Table 4-10 shows the 27 USB requests that share the USB Interrupt. Figur e4-1 shows the USB Interrupt logic; the bottom IRQ, EP8ISOERR, is expanded in the diagram to show the logic which is associated with each USB interrupt request. Table 4-10.
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EZ-USB FX2 Technical Reference Manual USB Interrupt 00 SUDAV 01 SOF 02 SUTOK EIE.0 FX2 "USB" Interrupt S R EXIF.4(rd) EXIF.4(0) 29 EP4ISOERR 30 EP6ISOERR USBERRIE.7 31 S EP8ISOERR USBERRIRQ.7 (1) R USBERRIRQ.7 (rd) Interrupt Request Latch INT2VEC 0 IV4 IV3 IV2 IV1 IV0 0 0 Figure 4-1. USB Interrupts Referring to the logic inside the dotted lines, each USB interrupt source has an interrupt request latch.
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If Autovectoring is enabled, the INT2VEC byte replaces the contents of address 0x0045 in the FX2’s program memory. This causes the FX2 to automatically vector to a different address for each USB interrupt source. This mechanism is explained in detail in Section 4.5. "USB-Interrupt Autovectors." Due to the OR gate in Figure 4-1, assertion of any of the individual USB interrupt sources sets the FX2’s “main” USB Interrupt request bit (EXIF.4). This main USB interrupt is enabled by setting EIE.0 to 1.
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EZ-USB FX2 Technical Reference Manual Figure 4-2 illustrates a typical USB ISR for endpoint 2-IN. USB_ISR: push push push push push push ; mov clr mov ; mov mov movx ; ; (service the ; pop pop pop pop pop pop ; reti dps dpl dph dpl1 dph1 acc a,EXIF acc.4 EXIF,a ; FIRST clear the USB (INT2) interrupt request ; Note: EXIF reg is not bit-addressable dptr,#USBERRIRQ ; now clear the USB interrupt request a,#10000000b ; use EP8ISOERR as example @dptr,a interrupt here) acc dph1 dpl1 dph dpl dps Figure 4-2.
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SUTOK and SUDAV are supplied to the FX2 by CONTROL endpoint zero. The first portion of a USB CONTROL transfer is the SETUP stage shown in Figure 4-3 (a full CONTROL transfer is shown in Figure 2-1). When the FX2 decodes a SETUP packet, it asserts the SUTOK (SETUP Token) Interrupt Request. After the FX2 has received the eight bytes error-free and copied them into the eight internal registers at SETUPDAT, it asserts the SUDAV Interrupt Request.
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EZ-USB FX2 Technical Reference Manual 4.4.2.7 Endpoint Interrupts These interrupts are asserted when an endpoint requires service. For an OUT endpoint, the interrupt request signifies that OUT data has been sent from the host, validated by the FX2, and is in the endpoint buffer memory. For an IN endpoint, the interrupt request signifies that the data previously loaded by the FX2 into the IN endpoint buffer has been read and validated by the host, making the IN endpoint buffer ready to accept new data.
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4.4.2.10 ERRLIMIT Interrupt This interrupt is asserted when the USB error-limit counter has exceeded the preset error limit threshold. See Section 8.6.3.3 for full details. 4.4.2.11 EPxISOERR Interrupt These interrupts are asserted when an ISO data PID is missing or arrives out of sequence, or when an ISO packet is dropped because no buffer space is available (to receive an OUT packet) or no data is available to be sent (from an IN buffer). 4.
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EZ-USB FX2 Technical Reference Manual Table 4-13.
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4.5.1 USB Autovector Coding To employ autovectoring for the USB interrupt: 1. Insert a jump instruction at 0x0043 to a table of jump instructions to the various USB interrupt service routines. Make sure the jump table starts on a 0x0100-byte page boundary. 2. Code the jump table with jump instructions to each individual USB interrupt service routine.
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EZ-USB FX2 Technical Reference Manual 4.6 I²C-Compatible Bus Interrupt EIE.1 DONE RD or WR I2DAT register S S R R EXIF.5(rd) I2CCompatible Bus Interrupt 2 I C-Compatible Bus Interrupt Request EXIF.5(0) I2CS 0xE678 START STOP LASTRD ID1 ID0 BERR ACK DONE I2DAT 0xE679 D7 D6 D5 D4 D3 D2 D1 D0 Figure 4-6. I²C-Compatible Bus Interrupt-Enable Bits and Registers Chapter 13, "Input/Output" describes the interface to the FX2’s I²C-Compatible Bus controller.
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4.7 FIFO/GPIF Interrupt (INT4) Just as the USB Interrupt is shared among 27 individual USB-interrupt sources, the FIFO/GPIF interrupt is shared among 14 individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, like the USB Interrupt, can employ autovectoring. Table 4-14 shows the priority and INT4VEC values for the 14 FIFO/GPIF interrupt sources. Table 4-14.
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EZ-USB FX2 Technical Reference Manual Important It is important in any FIFO/GPIF Interrupt Service Routine (ISR) to clear the main INT4 Interrupt before clearing the individual FIFO/GPIF interrupt request latch. This is because as soon as the individual FIFO/GPIF interrupt is cleared, any pending FIFO/GPIF interrupt will immediately try to generate another main FIFO/GPIF Interrupt. If the main INT4 IRQ bit has not been previously cleared, the pending interrupt will be lost.
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As shown in Table 4-16, the jump table contains a series of jump instructions, one for each individual FIFO/GPIF Interrupt source’s ISR. Table 4-16.
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EZ-USB FX2 Technical Reference Manual FIFO/GPIF Interrupt Vector 0x0053 LJMP 0x0054 04 0x0055 A4 INT4VEC FIFO_GPIF_Jmp_Table: 0x0480 EP4FF_ISR Automatically copied by FX2 0x04A4 LJMP EP4FF_ISR A4 0x04A5 01 0x04A6 19 0x0321 Figure 4-7. The FIFO/GPIF Autovector Mechanism in Action Figure 4-7 illustrates an ISR that services EP4’s Full Flag. When EP4 goes full, the FX2 asserts the FIFO/GPIF interrupt request, vectoring to location 0x0053.
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Chapter 5 Memory 5.1 Introduction Memory organization in the FX2 is similar, but not identical, to that of the standard 8051. There are three distinct memory areas: Internal Data Memory, External Data Memory, and External Program Memory. As will be explained below, “External” memory is not necessarily external to the FX2 chip. 5.2 Internal Data RAM As shown in Figure 5-1, the FX2’s Internal Data RAM is divided into three distinct regions: the “Lower 128”, the “Upper 128”, and “SFR Space”.
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EZ-USB FX2 Technical Reference Manual 5.2.1 The Lower 128 The Lower 128 occupies Internal Data RAM locations 0x00-0x7F. All of the Lower 128 may be accessed as general-purpose RAM, using either direct or indirect addressing (for more information on the FX2 addressing modes, see Chapter 12 "Instruction Set"). Two segments of the Lower 128 may additionally be accessed in other ways. • Locations 0x00-0x1F comprise four banks of 8 registers each, numbered R0 through R7.
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5.3 External Program Memory and External Data Memory The standard 8051 employs a Harvard architecture for its External memory; the program and data memories are physically separate. The FX2 uses a modified version of this memory model; offchip program and data memories are separate, but the on-chip program and data memories are unified in a Von Neumann architecture.
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EZ-USB FX2 Technical Reference Manual Note that only the data-memory space is reserved; program memory in the 0xE000-0xFFFF range is not reserved, so the 128-pin FX2 can access off-chip program memory in that range. 5.3.1 56- and 100-pin FX2 The 56- and 100-pin FX2 chips have no facility for adding off-chip program or data memory. Therefore, the Main RAM must serve as both program and data memory. To accomplish this, the FX2 reads the Main RAM using the logical OR of the PSEN and RD strobes.
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5.4 FX2 Memory Maps In s id e F X 2 O u ts id e F X 2 d a ta m e m o ry FFFF E200 E000 7.5 K ilobytes U S B regs and 4K E P buffers D a ta (R D ,W R ) 0.
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EZ-USB FX2 Technical Reference Manual On-chip FX2 memory consists of three RAM regions: • 0x0000-0x1FFF (Main RAM) • 0xE000-0xE1FF (Scratch RAM) • 0xE200-0xFFFF (Registers/Buffers) The 8K “Main RAM” occupies code-memory (PSEN) and data-memory (RD/WR) addresses 0x0000-0x1FFF. The 512-byte “Scratch RAM” occupies data-memory (RD/WR) addresses 0xE000-0xE1FF. 7.5K of control/status registers and endpoint buffers occupy data-memory (RD/WR) addresses 0xE200-0xFFFF.
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In s id e F X 2 O u ts id e F X 2 d a ta m e m o ry FFFF E200 E000 7.5 K ilobytes U S B regs and 4K E P buffers D a ta (R D ,W R ) 0.
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EZ-USB FX2 Technical Reference Manual Be careful to check the access time of external Flash or other code memory in this mode. The FX2 can stretch its RD and WR strobes to compensate for slow data memories, but it does not have the capability to stretch its PSEN signal to allow for slow code memories. At 48 MHz, an external code-memory chip must have an access time of approximately 44 ns or shorter (access-time parameters are given in the CY7C68013 data sheet). 5.
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5.6 On-Chip Data Memory at 0xE000-0xFFFF FFFF FC00 FBFF F800 F7FF F400 F3FF F000 E P 8 B uffer (1024) E P 6 B uffer (1024) E P 4 B uffer (1024) E P 2 B uffer (1024) EFFF R E S E R V E D (2048) E800 E7FF E7C0 E7BF E780 E77F E740 E73F E700 E6FF E600 E5FF E480 E47F E400 E P 1IN (64) E P 1O U T (64) E P 0 IN /O U T (64) U N A V A ILA B LE (64) R egisters (256) R E S E R V E D (384) G P IF waveform s (128) E3FF R E S E R V E D (512) E200 E1FF 8051 data (512) E000 Figure 5-4.
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EZ-USB FX2 Technical Reference Manual Page 5-10 EZ-USB FX2 Technical Reference Manual v2.
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Chapter 6 6.1 Power Management Introduction The USB host can suspend a device to put it into a power-down mode. When the USB signals a SUSPEND operation, the FX2 goes through a sequence of steps to allow the firmware first to turn off external power-consuming subsystems, and then to enter a low-power mode by turning off the FX2’s oscillator. Once suspended, the FX2 is awakened either by resumption of USB bus activity or by assertion of one of its two WAKEUP pins (provided that they’re enabled).
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EZ-USB FX2 Technical Reference Manual The FX2 enters and exits its Idle state independent of USB activity; in other words, the FX2 can enter the Idle state at any time, even when not connected to USB. The Idle state is “hooked into” the USB SUSPEND-RESUME mechanism using interrupts. An interrupt is automatically generated when the USB goes inactive for 3 milliseconds; FX2 firmware may respond to that interrupt by entering the Idle state to reduce power.
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6.2 USB Suspend 24 MHz STOP Oscillator PLL divider CLKOUT PCON.0 8051 No USB activity for 3 msec. Signal Resume (USBCS.0) USB "SUSPEND" Interrupt Write any value to SUSPEND register (0xE681) Figure 6-2. USB Suspend sequence A USB device recognizes a SUSPEND request as three milliseconds of the bus-idle (“J”) state. When the FX2 detects this condition, it asserts the USB interrupt (INT2) and the SUSPEND interrupt autovector (vector #3).
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EZ-USB FX2 Technical Reference Manual FX2 firmware responds to the SUSPEND interrupt by taking the following actions: 1. Perform any necessary housekeeping such as shutting off external power-consuming devices. 2. Set bit 0 of the PCON register. These actions put the FX2 into a low power ‘suspend’ state, as required by the USB Specification. 6.2.1 SUSPEND Register FX2 firmware can force the chip into its low-power mode at any time, even without detecting a 3-millisecond “J” state on the USB bus.
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Once in the low-power mode, there are three ways to wake up the FX2: • USB activity on the FX2’s DPLUS pin • Assertion of the WAKEUP pin • Assertion of the WU2 (“Wakeup 2”) pin These three wakeup sources may be individually enabled by setting the DPEN, WUEN, and WU2EN bits in the Wakeup Control register.
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EZ-USB FX2 Technical Reference Manual The Wakeup Interrupt Service Routine clears the interrupt request flag (using the ‘bit clear’ instruction, i.e. ‘clr EICON.4’), and then executes a ‘reti’ (return from interrupt) instruction. This causes the FX2 to continue program execution at the instruction following the one that set PCON.0 to initiate the power-down operation. About the Wakeup Interrupt The FX2 enters its idle state when it sets PCON.0 to 1.
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functions, the PA3 and WU2 functions are simultaneously active. However, the WU2 function has no effect unless enabled (by setting the WU2EN bit to 1). If WU2 is used as a wakeup pin, make sure to set PA3 as an input (OEA.3=0, the default state) to prevent PA3 from also driving the pin. The dual nature of the PA3/WU2 pin allows the FX2 to enter the low-power mode, then periodically awaken itself.
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EZ-USB FX2 Technical Reference Manual Page 6-8 EZ-USB FX2 Technical Reference Manual v2.
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Chapter 7 Resets 7.1 Introduction The FX2 chip has two internal resets: • Power-On Reset (POR), controlled by the RESET pin, which puts the FX2 in a known state. • CPU Reset, controlled by the FX2’s USB Core logic. The CPU Reset is always asserted (i.e., the CPU is always held in reset) while the FX2’s RESET pin is asserted.
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EZ-USB FX2 Technical Reference Manual 7.2 Power-On Reset (POR) An active-low input pin (RESET) resets the FX2 chip. Note that the term “Power-On Reset” refers to a reset initiated either by application of power or by assertion of the RESET pin. The RESET pin is normally connected to an external R-C network in order to ensure that, when power is first applied, the FX2 is held in reset until the operating parameters (Vcc voltage, crystal frequency, PLL frequency, etc.) stabilize.
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7.3 Releasing the CPU Reset Register bit CPUCS.0 resets the CPU. This bit is set to 1 at power-on, initially holding the CPU in reset. There are three ways that the CPUCS.0 bit can be cleared to 0, releasing the CPU from reset: • By the host, as the final step of a RAM download. • Automatically, at the end of an EEPROM load (assuming the EEPROM is correctly programmed). • Automatically, when external ROM is used (EA=1) and no “C0” or “C2” EEPROM is present.
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EZ-USB FX2 Technical Reference Manual • No “C0/C2” EEPROM is detected on the I² C-compatible bus. Under these conditions, the FX2 also sets the RENUM bit to 1, so the firmware will be responsible for responding to USB device requests. 7.4 CPU Reset Effects The USB host may reset the CPU at any time by downloading the value 0x01 to the CPUCS register. The host might do this, for example, in preparation for loading code overlays, effectively magnifying the size of the internal FX2 RAM.
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Note that the RENUM bit is unchanged after a USB bus reset. Therefore, if a device has ReNumerated™ and loaded a new personality, it retains the new personality through a USB bus reset. 7.6 FX2 Disconnect Although not strictly a “reset,” the disconnect-reconnect sequence used for ReNumeration™ affects the FX2 in ways similar to the other resets. When the FX2 simulates a disconnect-reconnect, the following occurs: • Endpoint STALL bits are cleared. • Data toggles are reset to 0.
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EZ-USB FX2 Technical Reference Manual Page 7-6 EZ-USB FX2 Technical Reference Manual v2.
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Chapter 8 Access to Endpoint Buffers 8.1 Introduction USB data enters and exits FX2 via endpoint buffers. In order to keep up with the high-speed 480 megabit/second transfer rates, external logic usually reads and writes this data by direct connection to the endpoint FIFOs without any participation by the FX2’s CPU. Chapter 9, "Slave FIFOs" and Chapter 10, "General Programmable Interface (GPIF)" give details about how external logic directly connects to the large endpoint FIFOs.
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EZ-USB FX2 Technical Reference Manual control of the FIFO interfaces described in Chapters 9 and 10, the CPU can access the large endpoints if necessary. 8.3 High-Speed and Full-Speed Differences FX2 operates at both full speed (12 Mbps) and high speed (480 Mbps). The data-payload-size and transfer-speed requirements differ between the two modes. FX2 architecture is optimized for high speed transfers: • Instead of many small endpoint buffers, FX2 provides a reduced number of large buffers.
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8.4 How the CPU Configures the Endpoints Endpoints are configured via the six registers shown in Table 8-2. Table 8-2.
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EZ-USB FX2 Technical Reference Manual – 01 = invalid – 10 = double (default) – 11 = triple “Buffering” refers to the number of RAM blocks available to the endpoint. With double buffering, for example, USB data can fill or empty an endpoint buffer at the same time that another packet from the same endpoint fills or empties from the external logic. This technique maximizes performance by saving each side, USB and external-logic interface, from waiting for the other side.
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For example, if EP2 is configured for triple-buffered 1024-byte operation, the firmware should access EP2 only at 0xF000-0xF3FF. The firmware should not access the EP4 or EP6 buffers in this configuration, since they don’t exist (the RAM space which they would normally occupy is used to implement the EP2 triple-buffering). 8.
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EZ-USB FX2 Technical Reference Manual HSNAK HSNAK is automatically set to 1 whenever the SETUP token of a CONTROL transfer arrives. The FX2 logic automatically NAKs the STATUS (handshake) stage of the CONTROL transfer until the firmware clears the HSNAK bit by writing “1” to it. This mechanism gives the firmware a chance to hold off subsequent transfers until it completes the actions required by the CONTROL transfer. Firmware must clear the HSNAK bit after servicing every CONTROL transfer.
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8.6.1.2 EP0BCH and EP0BCL These are the byte count registers for bytes sent as the optional data stage of a CONTROL transfer. Although the EP0 buffer is only 64 bytes wide, the byte count registers are 16 bits wide to allow using the Setup Data Pointer to send USB IN data records that consist of multiple packets.
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EZ-USB FX2 Technical Reference Manual 8.6.1.4 EP01STAT The BUSY bits in EP0CS, EP1OUTCS, and EP1INCS (described later in this chapter) are replicated in this SFR; they are provided here in order to allow faster access (via the MOV instruction rather than MOVX) to those bits. Three status bits are provided in the EP01STAT register; the status bits are the following: • EP1INBSY: 1 = EP1IN is busy • EP1OUTBSY: 1 = EP1OUT is busy • EP0BSY: 1 = EP0 is busy 8.6.1.
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STALL Firmware sets STALL=1 to instruct the FX2 to return the STALL PID (instead of ACK or NAK) in response to an EP1OUT transfer. The FX2 will continue to respond to EP1OUT transfers with the STALL PID until the firmware clears this bit. 8.6.1.6 EP1OUTBC Firmware may read this 7-bit register to determine the number of bytes (0-64) in EP1OUTBUF. Firmware writes any value to EP1OUTBC to arm an EP1OUT transfer. 8.6.1.7 EP1INCS This register is used to coordinate BULK or INTERRUPT transfers over EP1IN.
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EZ-USB FX2 Technical Reference Manual 8.6.2 Registers That Control EP2, EP4, EP6, EP8 In order to achieve the high transfer bandwidths required by USB 2.0’s high-speed mode, the FX2’s CPU should not participate in transfers to and from the “large” endpoints. Instead, those endpoints are usually connected directly to external logic (see Chapter 9 and Chapter 10 for details). Some applications, however, may require the firmware to have at least some small amount of control over the large endpoints.
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These registers do not affect full-speed (12 Mbps) operation; full-speed isochronous transfers are always fixed at one packet per frame. Table 8-6. Isochronous IN Packets per Microframe, High-Speed Only INPPF1 INPPF0 Packets 0 0 Invalid 0 1 1 1 0 2 1 1 3 8.6.2.3 EP2CS, EP4CS, EP6CS, EP8CS Because the four large FX2 endpoints offer double, triple or quad buffering, a single BUSY bit is not sufficient to convey the state of these endpoint buffers.
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EZ-USB FX2 Technical Reference Manual transfer logic. As soon as one buffer becomes available, FULL will be cleared to 0 and NPAK will decrement by one, indicating that all but one of the buffers are committed to USB (i.e., one is available for firmware access). As IN buffers are transferred over USB, NPAK decrements to indicate the number still pending, until all are sent and NPAK=0. EMPTY While FULL and EMPTY apply to transfers in both directions, EMPTY is more useful for OUT transfers.
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the packet to the outside interface (the “output FIFO”), or discard it. The firmware might, for example, inspect a packet header to make this skip/commit decision. To enable this “hook”, the AUTOOUT bit is cleared to 0.
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EZ-USB FX2 Technical Reference Manual 8.6.3.1 IBNIE, IBNIRQ, NAKIE, NAKIRQ These registers contain the interrupt-enable and interrupt-request bits for two endpoint conditions, IN-BULK-NAK and PING. IN-BULK-NAK (IBN) When the host requests an IN packet from an FX2 BULK endpoint, the endpoint NAKs (returns the NAK PID) until the endpoint buffer is filled with data and armed for transfer, at which point the FX2 answers the IN request with data.
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PING PING is the “flip side” of IBN; it’s used for high speed (480 Mbits/sec) BULK OUT transfers. When operating at full speed (USB 1.1 spec), every host OUT transfer consists of the OUT PID and the endpoint data, even if the endpoint is NAKing (not ready). While the endpoint is not ready, the host repeatedly sends all the OUT data; if it’s repeatedly NAK’d, bus bandwidth is wasted. USB 2.0 introduced a new mechanism, called PING, that makes better use of bus bandwidth for “unready” BULK OUT endpoints.
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EZ-USB FX2 Technical Reference Manual For the small endpoints (EP0 and EP1IN/OUT), these conditions are synonymous with the endpoint BUSY bit making a 1-to-0 transition (busy to not-busy). As with all FX2 interrupts, this one is enabled by writing a “1” to its enable bit, and the interrupt flag by writing a “1” to it. Do not attempt to clear an IRQ bit by reading the IRQ register, ORing its contents with a bit mask (e.g. 00010000), then writing the contents back to the register.
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• After a configuration changes (i.e., after the host issues a Set Configuration request). • After an interface’s alternate setting changes (i.e., after the host issues a Set Interface request). • After the host sends a Clear Feature - Endpoint Stall request to an endpoint. For the first two, the firmware must clear the data toggle bits for all endpoints contained in the affected interfaces. For the third, only one endpoint’s data toggle bit is cleared.
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EZ-USB FX2 Technical Reference Manual The Setup Data Pointer automates this process of returning IN data over EP0, simplifying the firmware. For the Setup Data Pointer to work properly, EP0’s MaxPacketSize must be set to 64. Table 8-8 lists the registers which configure the Setup Data Pointer. Table 8-8.
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8.7.1 Transfer Length When the host makes any EP0IN request, the FX2 respects the following two length fields: • the requested number of bytes (from the last two bytes of the SETUP packet received from the host) • the available number of bytes, supplied either as a length field in the actual descriptor (SDPAUTO=1) or in EP0BCH:L (SDPAUTO=0) In accordance with the USB Specification, the FX2 sends the smaller of these two length fields. 8.7.
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EZ-USB FX2 Technical Reference Manual Most of the Autopointer registers are in SFR Space for quick access; the data registers are available only in External Data space. Table 8-9.
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Chapter 9 Slave FIFOs 9.1 Introduction Although some FX2-based devices may use the FX2’s CPU to process USB data directly (see Chapter 8 "Access to Endpoint Buffers"), most will use the FX2 simply as a conduit between the USB and external data-processing logic (e.g., an ASIC or DSP, or the IDE controller on a hard disk drive).
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EZ-USB FX2 Technical Reference Manual 9.2 Hardware Figure 9-1 illustrates the four slave FIFOs. The figure shows the FIFOs operating in 16-bit mode, although they can also be configured for 8-bit operation.
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9.2.1 Slave FIFO Pins The FX2 comes out of reset with its I/O pins configured in “Ports” mode, not “Slave FIFO” mode. To configure the pins for Slave FIFO mode, the IFCFG1:0 bits in the IFCONFIG register must be set to 11 (see Table 13-10, “IFCFG Selection of Port I/O Pin Functions" for details). When IFCFG1:0 = 11, the Slave FIFO interface pins are presented to the external master, as shown in Figure 9-2. IF CLK F LA G A F LA G B F LA G C FX2 S lave M ode F LA G D / S LC S # S LO E E XT.
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EZ-USB FX2 Technical Reference Manual 9.2.2 FIFO Data Bus (FD) The FIFO data bus, FD[x:0], can be either 8 or 16 bits wide. The width is selected via each FIFO’s WORDWIDE bit, (EPxFIFOCFG.0): • WORDWIDE=0: 8-bit mode. FD[7:0] replaces Port B. See Figure 9-4. • WORDWIDE=1: 16-bit mode. FD[15:8] replaces Port D and FD[7:0] replaces Port B. See Figure 9-5. At power-on reset, the FIFO data bus defaults to 16-bit mode (WORDWIDE = 1) for all FIFOs.
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FX2 R egisters S lave FIFO s D evice P ins 30/48M H z IFC LK 5 - 48M H z FIFO A D R [1:0] E P 2FIFO B U F E P 4FIFO B U F E P 6FIFO B U F E P 8FIFO B U F EP2 EP4 EP6 EP8 FLA G A FLA G B FLA G C FLA G D /S LC S # S LO E S LR D S LW R P K TE N D FD [15:0] Figure 9-5. 16-bit Mode Slave FIFOs, WORDWIDE=1 9.2.3 Interface Clock (IFCLK) The slave FIFO interface can be clocked from either an internal or an external source.
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EZ-USB FX2 Technical Reference Manual IFC FG .6 30 M H z 48 M H z IFC FG .4 0 1 IFC FG .5 0 1 IFC LK P in IFC FG .7 IFC FG .4 Internal IFC LK S ignal 1 0 0 1 Figure 9-6. IFCLK Configuration Internal IFCLK Signal Inverted IFCLK Output FIFO Flag FX2 Asserts Flag ts Master Samples Flag Figure 9-7. Satisfying Setup Timing by Inverting the IFCLK Output 9.2.
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equally useful for either type of endpoint (it can, for instance, give advance warning that an OUT endpoint is almost empty or that an IN endpoint is almost full). The FLAGA, FLAGB, and FLAGC pins can operate in either of two modes: Indexed or Fixed, as selected via the PINFLAGSAB and PINFLAGSCD registers. The FLAGD pin operates in Fixed mode only. Each pin is configured independently; some pins can be in Fixed mode while others are in Indexed mode. See Chapter 15, "Registers," for complete details.
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EZ-USB FX2 Technical Reference Manual 9.2.5 Control Pins (SLOE, SLRD, SLWR, PKTEND, FIFOADR[1:0]) The Slave FIFO “control” pins are SLOE (Output Enable), SLRD (Read), SLWR (Write), PKTEND (Packet End), and FIFOADR[1:0] (FIFO Select). “Read” and “Write” are from the external master’s point of view; the external master reads from OUT endpoints and writes to IN endpoints. See Figure 9-9. Read — SLOE and SLRD: In synchronous mode (IFCONFIG.
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PKTEND: An external master asserts the PKTEND pin to commit an IN packet to USB regardless of the packet’s length. PKTEND is usually used when the master wishes to send a “short” packet (i.e., a packet smaller than the size specified in the EPxAUTOINLENH:L registers). For example: Assume that EP4AUTOINLENH:L is set to the default of 512 bytes.
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EZ-USB FX2 Technical Reference Manual 9.2.6 Slave FIFO Chip Select (SLCS) The “Slave FIFO Chip Select” pin (SLCS) is an alternate function of pin PA7; it’s enabled via the PORTACFG.6 bit (see Section 13.3.1, "Port A Alternate Functions"). The SLCS pin allows external logic to effectively remove the FX2 from the FIFO Data bus, in order to, for example, share that bus among multiple slave devices.
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Full State 3 Launch Done State 2 State 1 State 4 Figure 9-11. State Machine Example: Synchronous FIFO Writes IFC LK FA D D R 0 FA D D R 1 FLA G B - FU LL M aster S elects E P 8 E P 8 N ot E m pty FLA G C - E M P TY S LW R FD [15:0] Z N N +1 P K TE N D Figure 9-12. Timing Example: Synchronous FIFO Writes, Waveform 1 Chapter 9.
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EZ-USB FX2 Technical Reference Manual IFC LK FA D D R 0 C ore A uto FA D D R 1 C om m its P kt FLA G B - FU LL A U TO IN =1 FLA G C - E M P TY S LW R FD [15:0] 510 511 512 P K TE N D Figure 9-13. Timing Example: Synchronous FIFO Writes, Waveform 2 IFC LK FA D D R 0 FA D D R 1 FLA G B - FU LL FLA G C - E M P TY D ata N ot W ritten S LW R FD [15:0] 815 816 N P K TE N D M aster M anually C om m its S hort Pkt Figure 9-14.
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9.2.8 Implementing Synchronous Slave FIFO Reads IFC LK 5-48M H z FIFO A D R [1:0] FLA G B FU LL FLA G C E M P TY S LO E FX 2 Slave M ode EX T . M aster S LR D FD [15:0] Figure 9-15. Interface Pins Example: Synchronous FIFO Reads Typically, the sequence of events for the external master is: IDLE: When read event occurs, transition to State 1. STATE 1: Point to OUT FIFO, assert FIFOADR[1:0], transition to State 2. STATE 2: Assert SLOE.
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EZ-USB FX2 Technical Reference Manual IFC LK FA D D R 0 FA D D R 1 FLA G B - FU LL S elects E P 2 A sse rts S LO E then R eads First B yte in FIFO FLA G C - E M P TY Increm ents to N ext B yte in FIFO S LO E S LR D Z FD [15:0] N N +1 Figure 9-17. Timing Example: Synchronous FIFO Reads, Waveform 1 IFC LK FA D D R 0 FA D D R 1 FLA G B - FU LL E P 2 E m pty FLA G C - E M P TY R eads 1023 B yte in FIFO S LO E R eads Last B yte in FIFO S LR D FD [15:0] 1023 1024 Z Figure 9-18.
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9.2.9 Implementing Asynchronous Slave FIFO Writes FIFO A D R [1:0] FLA G B FU LL FLA G C E M P TY S LW R FX 2 Slave M ode FD [15:0] EX T . M aster P K TE N D Figure 9-19. Interface Pins Example: Asynchronous FIFO Writes Typically, the sequence of events for the external master is: IDLE: When write event occurs, transition to State 1. STATE 1: Point to IN FIFO, assert FIFOADR[1:0], transition to State 2.
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EZ-USB FX2 Technical Reference Manual IFC LK FA D D R 0 FA D D R 1 FLA G B - FU LL FLA G C - E M P TY S LW R FD [15:0] Z N N +1 P K TE N D Figure 9-21. Timing Example: Asynchronous FIFO Writes Page 9-16 EZ-USB FX2 Technical Reference Manual v2.
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9.2.10 Implementing Asynchronous Slave FIFO Reads FIFO A D R [1:0] FLA G B FU LL FLA G C E M P TY S LO E FX 2 Slave M ode S LR D EX T . M aster FD [15:0] Figure 9-22. Interface Pins Example: Asynchronous FIFO Reads Typically, the sequence of events for the external master is: IDLE: When read event occurs, transition to State 1. STATE 1: Point to OUT FIFO, assert FIFOADR[1:0], transition to State 2. STATE 2: If Empty flag is false (FIFO not empty), transition to State 3 else remain in State 2.
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EZ-USB FX2 Technical Reference Manual IFC LK FA D D R 0 FA D D R 1 FLA G B - FU LL FLA G C - E M P TY S LO E S LR D FD [15:0] Z N N +1 Figure 9-24. Timing Example: Asynchronous FIFO Reads Page 9-18 EZ-USB FX2 Technical Reference Manual v2.
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9.3 Firmware This section describes the interface between FX2 firmware and the FIFOs. More information is available in Chapter 8, "Access to Endpoint Buffers." Table 9-3.
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EZ-USB FX2 Technical Reference Manual FX2 Registers Slave FIFOs Device Pins 30/48MHz IFCLK 5 - 48MHz FIFOADR[1:0] EP2FIFOBUF EP4FIFOBUF EP6FIFOBUF EP8FIFOBUF EP2 EP4 EP6 EP8 FLAGA FLAGB FLAGC FLAGD/SLCS# SLOE SLRD SLWR PKTEND FD[15:0] Figure 9-25. EPxFIFOBUF Registers 9.3.2 EPx Memories The slave FIFOs connect external logic to the FX2’s four endpoint memories (EP2, EP4, EP6, and EP8). These endpoint memories have the following programmable features: 1.
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8051 Registers Slave FIFOs Device Pins 30/48MHz IFCLK 5 - 48MHz FIFOADR[1:0] EP2FIFOBUF EP4FIFOBUF EP6FIFOBUF EP8FIFOBUF EP2 EP4 EP6 EP8 FLAGA FLAGB FLAGC FLAGD/SLCS# SLOE SLRD SLWR PKTEND FD[15:0] Figure 9-26. EPx Memories 9.3.3 Slave FIFO Programmable-Level Flag (PF) Each FIFO’s programmable-level flag (PF) asserts when the FIFO reaches a user-defined fullness threshold. That threshold is configured as follows: 1. For OUT packets: The threshold is stored in PFC12:0.
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EZ-USB FX2 Technical Reference Manual 9.3.4 Auto-In / Auto-Out Modes The FX2 FIFOs can be configured to commit packets to/from USB automatically. For IN endpoints, Auto-In Mode allows the external logic to stream data into a FIFO continuously, with no need for it or the FX2 firmware to packetize the data or explicitly signal the FX2 to send it to the host.
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TD_Init(): … … … … … REVCTL = 0x03; // MUST set REVCTL.0 and REVCTL.1 to 1 SYNCDELAY; SYNCDELAY; EP8CFG = 0xE0; // EP8 is DIR=IN, TYPE=BULK SYNCDELAY; FIFORESET = 0x80; // Reset the FIFO SYNCDELAY; FIFORESET = 0x08; SYNCDELAY; FIFORESET = 0x00; SYNCDELAY; EP8FIFOCFG = 0x0C; // EP8 is AUTOOUT=0, AUTOIN=1, ZEROLEN=1, WORDWIDE=0 SYNCDELAY; EP8AUTOINLENH = 0x02; // Auto-commit 512-byte packets SYNCDELAY; EP8AUTOINLENL = 0x00; … … … … … Figure 9-29. TD_Init Example: Configuring AUTOIN = 1 9.3.
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EZ-USB FX2 Technical Reference Manual 9.3.6 CPU Access to OUT Packets, AUTOOUT = 0 In some systems, it may be desirable to allow the FX2’s CPU to participate in the transfer of data between the host and the slave FIFOs. To configure a FIFO for this “Manual-Out” mode, the AUTOOUT bit in the appropriate EPxFIFOCFG register must be cleared to 0 (see Figure 9-31).
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E PxB C H :L C PU skip = 0 H ost U SB D ata S lave M aster skip = 1 AUTOOUT = 0 Figure 9-32. Skip, Commit, or Source (AUTOOUT=0) TD_Poll(): … … … … … if( !( EP2468STAT & 0x01 ) ) { // EP2EF=0 when FIFO NOT empty, host sent packet OUTPKTEND = 0x02; // SKIP=0, pass buffer on to master } … … … … … Figure 9-33.
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EZ-USB FX2 Technical Reference Manual TD_Poll(): … … … … … if( EP24FIFOFLGS & 0x02 ) { SYNCDELAY; // FIFORESET = 0x80; // nak all OUT pkts. from host SYNCDELAY; // FIFORESET = 0x02; // advance all EP2 buffers to cpu domain SYNCDELAY; // EP2FIFOBUF[0] = 0xAA; // create newly sourced pkt. data SYNCDELAY; // EP2BCH = 0x00; SYNCDELAY; // EP2BCL = 0x01; // commit newly sourced pkt. to interface fifo // beware of "left over" uncommitted buffers SYNCDELAY; // OUTPKTEND = 0x82; // skip uncommitted pkt.
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TD_Init(): … … … … … REVCTL = 0x03; SYNCDELAY; SYNCDELAY; EP2CFG = 0xA2; SYNCDELAY; EP2FIFOCFG = 0x00; // MUST set REVCTL.0 and REVCTL.1 to 1 // EP2 is DIR=OUT, TYPE=BULK, SIZE=512, BUF=2x // EP2 is AUTOOUT=0, AUTOIN=0, ZEROLEN=0, WORDWIDE=0 // OUT endpoints do NOT come up armed SYNCDELAY; OUTPKTEND = 0x82; // arm first buffer by writing OUTPKTEND w/skip=1 SYNCDELAY; OUTPKTEND = 0x82; // arm second buffer by writing OUTPKTEND w/skip=1 … … … … … Figure 9-36.
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EZ-USB FX2 Technical Reference Manual I/O B usy CPU H ost USB D ata P ath S lave M aster A U TO IN =1 Figure 9-38. Master Writes Directly to Host, AUTOIN = 1 I/O B usy CPU H ost USB D ata P ath S lave M aster A U TO IN =0 or A U TO IN =1 Figure 9-39. Firmware Intervention, AUTOIN = 0 or 1 Page 9-28 EZ-USB FX2 Technical Reference Manual v2.
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TD_Poll(): … … … … … if( source_pkt_event ) { // 100-msec background timer fired if( holdoff_master( ) ) { // signaled “busy” to master successful while( !( EP68FIFOFLGS & 0x20 ) ) { // EP8EF=0, when buffer not empty ; // wait ‘til host takes entire FIFO data } FIFORESET = 0x80; SYNCDELAY; FIFORESET = 0x06; SYNCDELAY; FIFORESET = 0x00; EP8FIFOBUF[ EP8FIFOBUF[ EP8FIFOBUF[ EP8FIFOBUF[ 0 1 2 3 ] ] ] ] = = = = // initiate the “source packet” sequence 0x02; 0x06; 0x07; 0x03; // // // // , packet star
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EZ-USB FX2 Technical Reference Manual 9.3.8 Access to IN Packets, AUTOIN=0 In some systems, it may be desirable to allow the FX2’s CPU to participate in every data-transfer between the external master and the host. To configure a FIFO for this “Manual-In” mode, the AUTOIN bit in the appropriate EPxFIFOCFG register must be cleared to 0. In Manual-In mode, FX2 firmware can commit, skip, or edit packets sent by the external master, and it may also source packets directly.
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TD_Poll(): … … … … … if( master_finished_xfr( ) ) { // modify the data EP8FIFOBUF[ 0 ] = 0x02; // , packet start of text msg EP8FIFOBUF[ 7 ] = 0x03; // , packet end of text msg SYNCDELAY; EP8BCH = 0x00; SYNCDELAY; EP8BCL = 0x08; // pass buffer on to host } … … … … … Figure 9-43. TD_Poll Example, AUTOIN=0, Editing a Packet via EPxBCH:L 9.3.9 Auto-In / Auto-Out Initialization Enabling Auto-In transfers between slave FIFO and endpoint Typically, a FIFO is configured for Auto-In mode as follows: 1.
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EZ-USB FX2 Technical Reference Manual 9.3.10 Auto-Mode Example: Synchronous FIFO IN Data Transfers TD_Init(): REVCTL = 0x03; // MUST set REVCTL.0 and REVCTL.
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9.3.11 Auto-Mode Example: Asynchronous FIFO IN Data Transfers The initialization code is exactly the same as for the synchronous-transfer example in Section 9.3.10, but with IFCLK configured for internal use at a rate of 48 MHz and the ASYNC bit set to 1. Figure 9-45 shows the one-line modification that’s needed.
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EZ-USB FX2 Technical Reference Manual Page 9-34 EZ-USB FX2 Technical Reference Manual v2.
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Chapter 10 General Programmable Interface (GPIF) 10.1 Introduction The General Programmable Interface (GPIF) is an internal master to the FX2’s endpoint FIFOs. It replaces the external “glue” logic which might otherwise be required to build an interface between the FX2 and the outside world. At the GPIF’s core is a programmable state machine which generates up to six “control” and nine “address” outputs, and accepts six external and two internal “ready” inputs.
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EZ-USB FX2 Technical Reference Manual chapter will describe the structure of the Waveform Descriptors in some detail, knowledge of that structure is usually not necessary. The GPIFTool simply hides the complexity of the Waveform Descriptors; it doesn’t compromise the programmer’s control over the GPIF in any way.
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S0 GADR[8:0] FD[15:0] A S1 S2 S3 S4 S5 S6 A+1 Z VALID Z CTL0 RDY0 Figure 10-2. Example GPIF Waveform 10.1.1 Typical GPIF Interface The GPIF allows the EZ-USB FX2 to connect directly to external peripherals such as ASICs, DSPs, or other digital logic that uses an 8- or 16-bit parallel interface. The GPIF provides external pins that can operate as outputs (CTL[5:0]), inputs (RDY[5:0]), Data bus (FD[15:0]), and Address Lines (GPIFADR[8:0]).
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EZ-USB FX2 Technical Reference Manual G P IF A D R [ 8 : 0 ] IF C L K F D [1 5 :0 ] FX2 M a s te r Mode C T L [5 :0 ] P e r ip h e r a l R D Y [5 :0 ] P O R T I/O G S T A T E [2 :0 ] D ebug Figure 10-3. EZ-USB FX2 Interfacing to a Peripheral The following sections detail the features available and steps needed to create an efficient GPIF design.
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10.2 Hardware Table 10-1 lists the registers associated with the GPIF hardware; a detailed description of each register may be found in Chapter 15, "Registers." Table 10-1.
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EZ-USB FX2 Technical Reference Manual The Ready Input pins (RDY[5:0]) are sampled by the GPIF and can force a transaction to wait (inserting wait states), continue, or repeat until they’re in a particular state. The GPIF Data Bus is a collection of the FD[15:0] pins. • An 8-bit wide GPIF interface uses pins FD[7:0]. • A 16 bit-wide GPIF interface uses pins FD[15:0]. The GPIF Address lines (GPIFADR[8:0]) can generate an incrementing address as data is transferred.
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10.2.3 Six Control OUT Signals The 100- and 128-pin FX2 packages bring out all six Control Output pins, CTL[5:0]. The 56-pin package brings out three of these signals, CTL[2:0]. CTLx waveform edges can be programmed to make transitions as often as once per IFCLK clock (once every 20.8 ns if IFCLK is running at 48MHz). By default, these signals are driven high. 10.2.3.
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EZ-USB FX2 Technical Reference Manual 10.2.6 Three GSTATE OUT signals Three GPIF State lines, GSTATE[2:0], are available as an alternate configuration of PORTE[2:0]. These default to general-purpose inputs; setting GSTATE (IFCONFIG.2) to 1 selects the alternate configuration and overrides PORTECFG[2:0] bit settings. The GSTATE[2:0] pins output the current GPIF State number; this feature is typically used only while debugging GPIF waveforms. 10.2.
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When IFCLK is configured as an input, the minimum external frequency that can be applied to it is 5 MHz. IFC FG .6 30 M H z 48 M H z IFC FG .4 0 1 IFC FG .5 0 1 IFC LK P in IFC FG .7 IFC FG .4 Internal IFC LK S ignal 1 0 0 1 Figure 10-4. IFCLK Configuration Internal IFCLK Signal Inverted IFCLK Output Peripheral Signal Signal Asserted Signal Sampled ts Figure 10-5. Satisfying Setup Timing by Inverting the IFCLK Output Chapter 10.
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EZ-USB FX2 Technical Reference Manual 10.2.10 Connecting GPIF Signal Pins to Hardware The first step in creating the interface between the FX2’s GPIF and an external peripheral is to define the hardware interconnects. 1. Choose IFCLK settings. Decide whether to use an asynchronous or synchronous interface. If synchronous, choose either the internal or external interface clock. If internal, choose either 30 or 48 MHz; if external, ensure that the frequency of the external clock is in the range 5-48 MHz. 2.
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10.3 Programming the GPIF Waveforms Each GPIF Waveform Descriptor can define up to 7 States.
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EZ-USB FX2 Technical Reference Manual 10.3.1 The GPIF Registers Two blocks of registers control the GPIF state machine: • GPIF Configuration Registers — These registers configure the general settings and report the status of the interface. Refer to Chapter 15, "Registers," and the remainder of this chapter for details.
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To complete a GPIF transaction, the GPIF program must branch to the IDLE State, regardless of the State that the GPIF program is currently executing. For example, a GPIF Waveform might be defined by a program which contained only 2 programmed States, S0 and S1. The GPIF program would branch from S1 (or S0) to S7 when it wished to terminate. The state of the GPIF signals during the Idle State is determined by the contents of the GPIFIDLECS and GPIFIDLECTL registers.
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EZ-USB FX2 Technical Reference Manual • If TRICTL is 1, GPIFIDLECTL[7:4] are the output enables for the CTL[3:0] signals, and GPIFIDLECTL[3:0] are the output values for CTL[3:0]. CTL4 and CTL5 are unavailable in this mode. Table 10-5 illustrates this relationship. Table 10-5. Control Outputs (CTLn) During the IDLE State TRICTL 0 1 Control Output Output State Output Enable CTL0 GPIFIDLECTL.0 CTL1 GPIFIDLECTL.1 CTL2 GPIFIDLECTL.2 CTL3 GPIFIDLECTL.3 CTL4 GPIFIDLECTL.4 CTL5 GPIFIDLECTL.
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S0 GADR[8:0] FD[15:0] S1 S2 S3 S4 S5 S6 A Z VALID Z CTL0 Figure 10-7. Non-Decision Point (NDP) States Referring to Figure 10-7: In State 0: • FD[7:0] is programmed to be tristated. • CTL0 is programmed to be driven to a logic 1. In State 1: • FD[7:0] is programmed to be driven. • CTL0 is still programmed to be driven to a logic 1. In State 2: • FD[7:0] is programmed to be driven. • CTL0 is programmed to be driven to a logic 0. In State 3: • FD[7:0] is programmed to be driven.
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EZ-USB FX2 Technical Reference Manual Since all States in this example are coded as NDPs, the GPIF automatically branches from the last State (S6) to the Idle State (S7). This is the State in which the GPIF waits until the next GPIF waveform is triggered by the firmware. States 2 and 3 in the example are identical, as are States 5 and 6.
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S0 GADR[8:0] A FD[15:0] Z S1 S2 S3 S4 S5 VALID S6 Z CTL0 RDY0 Figure 10-8. One Decision Point: Wait States Inserted Until RDY0 Goes Low S0 GADR[8:0] A FD[15:0] Z S1 S2 S3 S4 VALID S5 S6 Z CTL0 RDY0 Figure 10-9. One Decision Point: No Wait States Inserted: RDY0 is Already Low at Decision Point I1 In Figure 10-8 and Figure 10-9, there is a single Decision Point defined as State 1.
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EZ-USB FX2 Technical Reference Manual In Figure 10-8, the GPIF remains in S1 until the RDY0 signal goes low, then branches to S2. Figure 10-9 illustrates the GPIF behavior when the RDY0 signal is already low when S1 is entered: The GPIF branches to S2. Although it appears in Figure 10-8 that the GPIF branches immediately from State 0 to State 2, this isn’t exactly true. Even if RDY0 is already low before the GPIF enters State 1, the GPIF spends one IFCLK cycle in State 1. 10.3.
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IFC LK G A D R [8:0] A A +1 A +2 A +3 FD [7:0] D D +1 D +2 D +3 C TL0 RDY0 NDP DP NDP D P , transitions to next interval when term s are m et D P , using re-execute control task feature… to loop on to itself until term s are m et Figure 10-10.
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EZ-USB FX2 Technical Reference Manual IFC LK G A D R [8:0] A A +1 FD [7:0] D D +1 C TL0 RDY0 NDP DP NDP D P , transitions to next interval when term s are m et D P , loop on to itself until term s are m et… control tasks execute on rising edge transition into D P only… Figure 10-12.
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10.3.4 State Instructions Each State’s characteristics are defined by a 4-byte State Instruction. The four bytes are named LENGTH / BRANCH, OPCODE, LOGIC FUNCTION, and OUTPUT. Note that the State Instructions are interpreted differently for Decision Points (DP = 1) and NonDecision Points (DP = 0).
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EZ-USB FX2 Technical Reference Manual Decision Point State Instruction (DP = 1) LENGTH / BRANCH Bit 7 Bit 6 Re-Execute Bit 5 x Bit 4 Bit 3 Bit 2 BRANCHON1 Bit 1 Bit 0 BRANCHON1 OPCODE 7 6 5 4 3 2 1 0 x x SGL GINT INCAD NEXT/ SGLCRC DATA DP = 1 2 1 0 LOGIC FUNCTION 7 6 5 LFUNC 4 3 TERMA TERMB OUTPUT (if TRICTL Bit = 1) 7 6 5 4 3 2 1 0 OE3 OE2 OE1 OE0 CTL3 CTL2 CTL1 CTL0 OUTPUT (if TRICTL Bit = 0) 7 6 5 4 3 2 1 0 x x CTL5 CTL4 CTL3 CTL2 CTL
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OPCODE Register: This register sets a number of State characteristics. SGL Bit: has no effect in a Single-Read or Single-Write waveform. In a FIFO waveform, it specifies whether a single-data transaction should occur (from/to the SGLDATAH:L or UDMA_CRCH:L registers), even in a FIFO-Write or FIFO-Read transaction. See also “NEXT/ SGLCRC”, below. 1 = Use SGLDATAH:L or UDMA_CRCH:L. 0 = Use the FIFO. GINT Bit: specifies whether to generate a GPIFWF interrupt during this State.
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EZ-USB FX2 Technical Reference Manual LOGIC FUNCTION Register: This register is used only in DP State Instructions. It specifies the inputs (TERMA and TERMB) and the Logic Function (LFUNC) to apply to those inputs. The result of the logic function determines the State to which the GPIF will branch (see also “LENGTH / BRANCH Register”, above). TERMA and TERMB bits: = 000: RDY0 = 001: RDY1 = 010: RDY2 = 011: RDY3 = 100: RDY4 = 101: RDY5 (or Transaction-Count Expiration, if GPIFREADYCFG.
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10.3.4.1 Structure of the Waveform Descriptors Up to four different Waveforms can be defined. Each Waveform Descriptor comprises up to 7 State Instructions which are loaded into the Waveform Registers as defined in this section. Table 10-6. Waveform Descriptor Addresses Waveform Descriptor Base XDATA Address 0 0xE400 1 0xE420 2 0xE440 3 0xE460 Within each Waveform Descriptor, the State Instructions are packed as described in Table 10-7, “Waveform Descriptor 0 Structure".
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EZ-USB FX2 Technical Reference Manual Table 10-7.
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TD_Init(): … … … … … GpifInit(); // Configures GPIF from GPIFTool generated waveform data // TODO: configure other endpoints, etc. here // TODO: arm OUT buffer(s) here // setup INT4 as internal source for GPIF interrupts // using INT4CLR (SFR), automatically enabled //INTSETUP |= 0x03; //Enable INT4 Autovectoring // SYNCDELAY; //GPIFIE = 0x03; // Enable GPIFDONE and GPIFWF interrupt(s) // SYNCDELAY; //EIE |= 0x04; // Enable INT4 ISR, EIE.
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EZ-USB FX2 Technical Reference Manual GPIFWFSELECT = InitData[ 5 ]; GPIFREADYSTAT = InitData[ 6 ]; // use dual autopointer feature... AUTOPTRSETUP = 0x07; // inc both pointers, // ...warning: this introduces pdata hole(s) // ...
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// Set EP2GPIF Transaction Count void Peripheral_SetEP2GPIFTC( WORD xfrcnt ) { SYNCDELAY; // EP2GPIFTCH = xfrcnt >> 8; // setup transaction count SYNCDELAY; // EP2GPIFTCL = ( BYTE )xfrcnt; } // Set EP4GPIF Transaction Count void Peripheral_SetEP4GPIFTC( WORD xfrcnt ) { SYNCDELAY; // EP4GPIFTCH = xfrcnt >> 8; // setup transaction count SYNCDELAY; // EP4GPIFTCL = ( BYTE )xfrcnt; } // Set EP6GPIF Transaction Count void Peripheral_SetEP6GPIFTC( WORD xfrcnt ) { SYNCDELAY; // EP6GPIFTCH = xfrcnt >> 8; // setup tr
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EZ-USB FX2 Technical Reference Manual // Set EP8GPIF Decision Point FIFO Flag Select (PF, EF, FF) void SetEP8GPIFFLGSEL( WORD DP_FIFOFlag ) { EP8GPIFFLGSEL = DP_FIFOFlag; } // Set EP2GPIF Programmable Flag STOP, overrides Transaction Count void SetEP2GPIFPFSTOP( void ) { EP2GPIFPFSTOP = 0x01; } // Set EP4GPIF Programmable Flag STOP, overrides Transaction Count void SetEP4GPIFPFSTOP( void ) { EP4GPIFPFSTOP = 0x01; } // Set EP6GPIF Programmable Flag STOP, overrides Transaction Count void SetEP6GPIFPFSTOP( vo
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{ static BYTE g_data = 0x00; while( !( GPIFTRIG & 0x80 ) ) { ; } // poll GPIFTRIG.7 Done bit // using register(s) in XDATA space, dummy read g_data = XGPIFSGLDATLX; // trigger GPIF // ...single byte read transaction while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit { ; } // using register(s) in XDATA space, *gdata = XGPIFSGLDATLNOX; // ...
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EZ-USB FX2 Technical Reference Manual ; } // trigger FIFO write transaction(s), using SFR GPIFTRIG = FIFO_EpNum; // R/W=0, EP[1:0]=FIFO_EpNum for EPx write(s) } // read byte(s)/word(s) from PERIPHERAL, using GPIF and EPxFIFO // if EPx WORDWIDE=0 then read byte(s) // if EPx WORDWIDE=1 then read word(s) void Peripheral_FIFORead( BYTE FIFO_EpNum ) { while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.
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10.4.1 Single-Read Transactions 8051 G P IF XD A TA D evice P ins * FD [7:0] 30/48M H z IFC LK 5 - 48M H z C LK XG P IFS G LD A TH /L 8051 G P IFA D R [8:0] W aveform D escriptors C TL[5:0] W F0 W F1 W F2 W F3 R D Y [5:0] G P IF XG P IFS G LD A TLX G P IF D O N E G P IFW F 8051 IN TR D Y * All EPx WORDWIDE bits must be cleared to 0 for 8-bit single transactions. If any of the EPx WORDWIDE bits are set to 1, then single transactions will be 16 bits wide. Figure 10-14.
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EZ-USB FX2 Technical Reference Manual IFCLK 0x00AB GADR[8:0] 0x80 hi-Z FD[7:0] hi-Z CTL0 RDY0 NDP NDP –i1I1 NDP i2 NDP i3 NDP i4 NDP Figure 10-15.
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To perform a Single-Read transaction: 1. Initialize the GPIF Configuration Registers and Waveform Descriptors. 2. Perform a dummy read of the XGPIFSGLDATLX register to start a single transaction. 3. Wait for the GPIF to indicate that the transaction is complete. When the transaction is complete, the DONE bit (GPIFIDLECS.7 or GPIFTRIG.7) will be set to 1. If enabled, a GPIFDONE interrupt will also be generated. 4.
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EZ-USB FX2 Technical Reference Manual #define #define #define #define #define PERIPHCS 0x00AB AOKAY 0x80 BURSTMODE 0x0000 TRISTATE 0xFFFF EVER ;; // prototypes void GpifInit( void ); // Set Address GPIFADR[8:0] to PERIPHERAL void Peripheral_SetAddress( WORD gaddr ) { if( gaddr < 512 ) { // drive GPIF address bus w/gaddr GPIFADRH = gaddr >> 8; SYNCDELAY; GPIFADRL = ( BYTE )gaddr; // setup GPIF address } else { // tristate GPIFADR[8:0] pins PORTCCFG = 0x00; // [7:0] as port I/O OEC = 0x00; // and as inputs
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void TD_Init( void ) { BYTE xdata periph_status; … … … … … GpifInit(); // Configures GPIF from GPIFTool generated waveform data // TODO: configure other endpoints, etc. here // TODO: arm OUT buffer(s) here // setup INT4 as internal source for GPIF interrupts // using INT4CLR (SFR), automatically enabled //INTSETUP |= 0x03; //Enable INT4 Autovectoring //SYNCDELAY; //GPIFIE = 0x03; // Enable GPIFDONE and GPIFWF interrupt(s) //SYNCDELAY; //EIE |= 0x04; // Enable INT4 ISR, EIE.
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EZ-USB FX2 Technical Reference Manual 10.4.2 Single-Write Transactions 8051 G P IF XD A TA D e vic e P in s * F D [7 :0 ] 3 0 /4 8 M H z IF C L K 5 - 48M Hz CLK X G P IF S G L D A T H /L 8051 G P IF A D R [8 :0 ] W a ve fo rm D e s c rip to rs C T L [5 :0 ] W F0 W F1 W F2 W F3 R D Y [5 :0 ] G P IF X G P IF S G L D A T L X G P IF D O N E G P IF W F 8 0 5 1 IN T R D Y * All EPx WORDWIDE bits must be cleared to zero for 8-bit single transactions.
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IFCLK 0x00AB GADR[8:0] hi-Z FD[7:0] 0x01 hi-Z CTL0 RDY0 NDP NDP –i1I1 NDP i2 NDP i3 NDP i4 NDP Figure 10-20.
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EZ-USB FX2 Technical Reference Manual ter to start a Single-Write transaction. In 8-bit mode, simply write the data to the XGPIFSGLDATLX register to start a Single-Write transaction. 3. Wait for the GPIF to indicate that the transaction is complete. When the transaction is complete, the DONE bit (GPIFIDLECS.7 or GPIFTRIG.7) will be set to 1. If enabled, a GPIFDONE interrupt will also be generated.
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void TD_Init( void ) { … … … … … GpifInit(); // Configures GPIF from GPIFTool generated waveform data // TODO: configure other endpoints, etc. here // TODO: arm OUT buffer(s) here // setup INT4 as internal source for GPIF interrupts // using INT4CLR (SFR), automatically enabled //INTSETUP |= 0x03; //Enable INT4 Autovectoring //SYNCDELAY; //GPIFIE = 0x03; // Enable GPIFDONE and GPIFWF interrupt(s) //SYNCDELAY; //EIE |= 0x04; // Enable INT4 ISR, EIE.
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EZ-USB FX2 Technical Reference Manual Each time through the Idle State, the GPIF will decrement the Transaction Count; when it expires, the waveform terminates and the DONE bit is set. Otherwise, the GPIF re-executes the entire Waveform Descriptor. In Long Transfer Mode, the DONE bit isn’t set until the Transaction Count expires. While the Transaction Count is active, the GPIF checks the Full Flag (for IN FIFOs) or the Empty Flag (for OUT FIFOs) on every pass through the Idle State.
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The GPIF Flag is tested only while transitioning through the Idle State, and it isn’t latched. If a GPIF Flag assertion occurs in one State, and the next State is a DP which tests the GPIF Flag and waits until it’s de-asserted before allowing the state machine to continue to the Idle State, the GPIF will automatically branch back to State 0 as though the GPIF Flag had never been asserted. 10.4.5.
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EZ-USB FX2 Technical Reference Manual G P IF TC E P xFIFO B UF TC =N 0x01 TC =N +1 0x02 TC =N +2 0x03 P eripheral data (P data) N N +1 0x01 … … i2 0x02 i2 N +2 0x03 i2 512 0xFF … … i2 … TC =512 0xFF Figure 10-25. Example FIFO-Read Transaction IFCLK 0x0000 GADR[8:0] hi-Z FD[7:0] Pdata++ hi-Z CTL0 RDY0 NDP NDP –i1I1 NDP i2 NDP i3 NDP i4 NDP Figure 10-26.
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State AddrMode 0 1 2 3 4 5 6 Same Val Same Val Same Val Same Val Same Val Same Val Same Val 7 DataMode No Data No Data Activate NO Data NO Data NO Data NO Data NextData SameData SameData SameData SameData SameData SameData SameData Int Trig IF/Wait No Int No Int No Int No Int No Int No Int No Int Wait 4 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Term A LFUNC Term B Branch1 Branch0 Re-execute CTL0 1 1 0 1 1 1 1 1 CTL1 1 1 1 1 1 1 1 1 CTL2 1 1
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EZ-USB FX2 Technical Reference Manual #define GPIFTRIGRD 4 #define #define #define #define GPIF_EP2 GPIF_EP4 GPIF_EP6 GPIF_EP8 0 1 2 3 #define BURSTMODE 0x0000 #define HSPKTSIZE 512 … … … … … // read(s) from PERIPHERAL, using GPIF and EPxFIFO void Peripheral_FIFORead( BYTE FIFO_EpNum ) { while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.
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void TD_Init( void ) { … … … … … GpifInit(); // Configures GPIF from GPIFTool generated waveform data // TODO: configure other endpoints, etc.
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EZ-USB FX2 Technical Reference Manual void TD_Poll( void ) { … … … … … if( !( EP68FIFOFLGS & 0x10 ) ) { // EP8FF=0 when buffer available // host is taking EP8 data fast enough Peripheral_FIFORead( GPIF_EP8 ); } if( gpifdone_event_flag ) { // GPIF currently pointing to EP8, last FIFO accessed if( !( EP2468STAT & 0x80 ) ) { // EP8F=0 when buffer available // modify the data EP8FIFOBUF[ 0 ] = 0x02; // , packet start of text msg EP8FIFOBUF[ 7 ] = 0x03; // , packet end of text msg SYNCDELAY; EP8BCH =
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TD_Init(): EP8CFG = 0xE0; // EP8 is DIR=IN, TYPE=BULK SYNCDELAY; EP8FIFOCFG = 0x0C; // EP8 is AUTOOUT=0, AUTOIN=1, ZEROLEN=1, WORDWIDE=0 SYNCDELAY; EP8AUTOINLENH = 0x02; // if AUTOIN=1, auto commit 512 byte packets SYNCDELAY; EP8AUTOINLENL = 0x00; TD_Poll(): // no code necessary to xfr data from master to host! // AUTOIN=1 and EP8AUTOINLEN=512 auto commits packets, // in 512 byte chunks. Figure 10-33.
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EZ-USB FX2 Technical Reference Manual TD_Poll(): … … … … … if( master_finished_longxfr( ) ) { // master currently points to EP8, last FIFO accessed if( !( EP68FIFOFLGS & 0x10 ) ) { // EP8FF=0 when buffer available INPKTEND = 0x08; // Firmware commits pkt // by writing #8 to INPKTEND release_master( EP8 ); } } … … … … … Figure 10-35.
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TD_Poll(): … … … … … if( source_pkt_event ) { // 100msec background timer fired if( holdoff_master( ) ) { // signaled “busy” to master successful while( !( EP68FIFOFLGS & 0x20 ) ) { // EP8EF=0, when buffer not empty ; // wait ‘til host takes entire FIFO data } // Reset FIFO 8.
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EZ-USB FX2 Technical Reference Manual 10.4.7.
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IFCLK 0x0000 GADR[8:0] hi-Z FD[7:0] Pdata++ hi-Z CTL0 RDY0 NDP NDP –i1I1 NDP i2 NDP i3 NDP i4 NDP Figure 10-40. FIFO-Write Transaction Waveform The above waveform executes until the Transaction Counter expires (until it counts to 512, in this example). The Transaction Counter is decremented and sampled on each pass through the Idle State. Each iteration of the waveform writes a data value from the FIFO to the FIFO Data bus, then decrements and checks the Transaction Counter.
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EZ-USB FX2 Technical Reference Manual Typically, when performing a FIFO-Write, only one “NextData” is needed in the waveform, since each execution of “NextData” increments the FIFO pointer. To perform a FIFO-Write Transaction: 1. In the GPIFTRIG register, set the RW bit to 0 and load EP1:0 with the appropriate value for the FIFO which is to receive the data. 2. Program the FX2 to detect completion of the transaction.
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void TD_Init( void ) { … … … … … GpifInit(); // Configures GPIF from GPIFTool generated waveform data // TODO: configure other endpoints, etc.
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EZ-USB FX2 Technical Reference Manual 10.4.8 Firmware access to OUT packets, (AUTOOUT=1) To achieve the maximum USB 2.0 bandwidth, the host and master are directly connected when AOUTOOUT=1; the CPU is bypassed and the OUT FIFO is automatically committed to the host: 8051 Host USB Data Path Slave GPIF Peripheral AUTOOUT=1, Long Transfer Mode Figure 10-45.
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10.4.9 Firmware access to OUT packets, (AUTOOUT = 0) 8051 skip=0 Host USB Data Slave GPIF Peripheral skip=1 AUTOOUT=0 Figure 10-48.
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EZ-USB FX2 Technical Reference Manual 2. It can skip packet(s) sent from the host to the master by writing the EPxBCL register with the SKIP bit (EPxBCL.7) set to 1 (see Figure 10-51). TD_Poll(): … … … … … if( !( EP24FIFOFLGS & 0x02 ) ) { // EP2EF=0 when FIFO “not” empty, host sent pkt. OUTPKTEND = 0x82; // SKIP=1, do NOT pass buffer on to master } … … … … … Figure 10-51. Skipping an OUT Packet by Writing OUTPKTEND w/SKIP=1 3.
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The master is not notified when a packet has been skipped by the firmware. The OUT FIFO is not committed to the host during a power-on-reset. In its initialization routine, therefore, the firmware should skip n packets (where n = 2, 3, or 4 depending on the buffering depth) in order to ensure that the entire FIFO is committed to the host. See Figure 10-53.
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EZ-USB FX2 Technical Reference Manual #define GPIFTRIGRD 4 #define #define #define #define GPIF_EP2 GPIF_EP4 GPIF_EP6 GPIF_EP8 0 1 2 3 #define BURSTMODE 0x0000 #define HSPKTSIZE 512 … … … … … // read(s) from PERIPHERAL, using GPIF and EPxFIFO void Peripheral_FIFORead( BYTE FIFO_EpNum ) { while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.
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void TD_Init( void ) { … … … … … GpifInit(); // Configures GPIF from GPIFTool generated waveform data // TODO: configure other endpoints, etc.
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EZ-USB FX2 Technical Reference Manual void TD_Poll( void ) { … … … … … if( ibn_event_flag ) { // host is asking for EP8 data Peripheral_SetEP8GPIFTC( HSPKTSIZE ); Peripheral_FIFORead( GPIF_EP8 ); ibn_event_flag = 0; } if( gpifdone_event_flag ) { // GPIF currently pointing to EP8, last FIFO accessed if( !( EP2468STAT & 0x80 ) ) { // EP8F=0 when buffer available INPKTEND = 0x08; // Firmware commits pkt // by writing #8 to INPKTEND gpifdone_event_flag = 0; } } // decide how GPIF transitions to DONE for FIFO T
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void TD_Poll( void ) { … … … … … if( !( EP68FIFOFLGS & 0x10 ) ) { // EP8FF=0 when buffer available // host is taking EP8 data fast enough Peripheral_SetEP8GPIFTC( HSPKTSIZE ); Peripheral_FIFORead( GPIF_EP8 ); } if( gpifdone_event_flag ) { // GPIF currently pointing to EP8, last FIFO accessed if( !( EP2468STAT & 0x80 ) ) { // EP8F=0 when buffer available // modify the data EP8FIFOBUF[ 0 ] = 0x02; // , packet start of text msg EP8FIFOBUF[ 7 ] = 0x03; // , packet end of text msg SYNCDELAY; EP8BCH = 0
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EZ-USB FX2 Technical Reference Manual Page 10-64 EZ-USB FX2 Technical Reference Manual v2.
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Chapter 11 CPU Introduction 11.1 Introduction The FX2’s CPU, an enhanced 8051, is fully described in Chapter 12, "Instruction Set", Chapter 13, "Input/Output", and Chapter 14, "Timers/Counters and Serial Interface". This chapter introduces the processor, its interface to the FX2 logic, and describes architectural differences from a standard 8051. Figure 11-1 is a block diagram of the FX2’s 8051-based CPU.
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EZ-USB FX2 Technical Reference Manual 11.2 8051 Enhancements The FX2 uses the standard 8051 instruction set, so it’s supported by industry-standard 8051 compilers and assemblers. Instructions execute faster on the FX2 than on the standard 8051: • Wasted bus cycles are eliminated; an instruction cycle uses only four clocks, rather than the standard 8051’s 12 clocks. • The FX2’s CPU clock runs at 12MHz, 24MHz, or 48MHz —up to four times the clock speed of the standard 8051.
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11.3 Performance Overview The FX2 has been designed to offer increased performance by executing instructions in a 4-clock bus cycle, as opposed to the 12-clock bus cycle in the standard 8051 (see Figure 11-2). This shortened bus timing improves the instruction execution rate for most instructions by a factor of three over the standard 8051 architectures. Some instructions require a different number of instruction cycles on the FX2 than they do on the standard 8051.
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EZ-USB FX2 Technical Reference Manual Single-Byte, Single-Cycle Instruction Timing PSEN FX2 AD0-AD7 PORT2 4 XTAL1 12 Standard 8051 ALE PSEN AD0-AD7 PORT2 Figure 11-2. FX2 to Standard 8051 Timing Comparison 11.4 Software Compatibility The FX2 is object-code-compatible with the industry-standard 8051 microcontroller. That is, object code compiled with an industry-standard 8051 compiler or assembler executes on the FX2 and is functionally equivalent.
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Table 11-2.
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EZ-USB FX2 Technical Reference Manual 11.6.3 Timed Access Protection The FX2 does not implement timed access protection and, therefore, does not implement the TA SFR. 11.6.4 Watchdog Timer The FX2 does not implement a watchdog timer. 11.6.5 Power Fail Detection The FX2 does not implement a power fail detection circuit. 11.6.6 Port I/O The FX2’s port I/O implementation is significantly different from that of the DS80C320, mainly because of the alternate functions shared with most of the I/O pins.
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11.7 EZ-USB FX2 Register Interface The FX2 peripheral logic (USB, GPIF, FIFOs, etc.) is controlled via a set of memory mapped registers and buffers at addresses 0xE400 through 0xFFFF. These registers and buffers are grouped as follows: • GPIF Waveform Descriptor Tables • General configuration • Endpoint configuration • Interrupts • Input/Output • USB Control • Endpoint operation • GPIF/FIFOs • Endpoint buffers These registers and their functions are described throughout this manual.
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EZ-USB FX2 Technical Reference Manual All other on-chip FX2 RAM (program/data memory, endpoint buffer memory, and the FX2 control registers) is addressed as though it were off-chip 8051 memory. FX2 firmware reads or writes these bytes as data using the MOVX (“move external”) instruction, even though the FX2 RAM and register set is actually inside the EZ-USB FX2 chip. Off-chip memory attached to the FX2 address and data buses (CY7C68013-128NC only) can also be accessed by the MOVX instruction.
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11.10 Interrupts All standard 8051 interrupts, plus additional interrupts, are supported by the FX2. Tabl e11-4 lists the FX2 interrupts. Table 11-4.
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EZ-USB FX2 Technical Reference Manual 11.12 Special Function Registers (SFR) The FX2 was designed to keep coding as standard as possible, to allow easy integration of existing 8051 software development tools. The FX2 SFR registers are summarized in Tabl e11-5. Standard 8051 SFRs are shown in normal type and FX2-added SFRs are shown in bold type. Full details of the SFRs can be found in Chapter 15, "Registers". Table 11-5.
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11.13 External Address/Data Buses The 128-pin version of the FX2 provides external, non-multiplexed 16-bit address and 8-bit data buses. This differs from the standard 8051, which multiplexes eight pins among three sources: I/O port 0, the external data bus, and the low byte of the external address bus. A standard 8051 system with external memory requires a demultiplexing address latch, strobed by the 8051 ALE (Address Latch Enable) pin.
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EZ-USB FX2 Technical Reference Manual Page 11-12 EZ-USB FX2 Technical Reference Manual v2.
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Chapter 12 Instruction Set 12.1 Introduction This chapter provides a technical overview and description of the FX2’s assembly-language instruction set. All FX2 instructions are binary-code-compatible with the standard 8051. The FX2 instructions affect bits, flags, and other status functions just as the 8051 instructions do. Instruction timing, however, is different both in terms of the number of clock cycles per instruction cycle and the number of instruction cycles used by each instruction.
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EZ-USB FX2 Technical Reference Manual Table 12-2.
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Table 12-2.
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EZ-USB FX2 Technical Reference Manual Table 12-2.
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Table 12-2.
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EZ-USB FX2 Technical Reference Manual The three LSBs of the Clock Control Register (CKCON, at SFR location 0x8E) control the stretch value; stretch values between zero and seven may be used. A stretch value of zero adds zero instruction cycles, resulting in MOVX instructions which execute in two instruction cycles. A stretch value of seven adds seven instruction cycles, resulting in MOVX instructions which execute in nine instruction cycles.
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12.1.3 Dual Data Pointers The FX2 employs dual data pointers to accelerate data memory block moves. The standard 8051 data pointer (DPTR) is a 16-bit pointer used to address external data RAM or peripherals. The FX2 maintains the standard data pointer as DPTR0 at the standard SFR locations 0x82 (DPL0) and 0x83 (DPH0); it is not necessary to modify existing code to use DPTR0. The FX2 adds a second data pointer (DPTR1) at SFR locations 0x84 (DPL1) and 0x85 (DPH1).
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EZ-USB FX2 Technical Reference Manual Table 12-4. PSW Register - SFR 0xD0 Bit PSW.7 Function CY - Carry flag. This is the unsigned carry bit. The CY flag is set when an arithmetic operation results in a carry from bit 7 to bit 8, and cleared otherwise. In other words, it acts as a virtual bit 8. The CY flag is cleared on multiplication and division. See the “PSW Flags Affected” column in Table 12-2. PSW.6 AC - Auxiliary carry flag.
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Chapter 13 Input/Output 13.1 Introduction The 56-pin FX2 package provides two input-output systems: • A set of programmable I/O pins • A programmable I²C-compatible bus controller The 100- and 128-pin packages additionally provide two programmable USARTs, which are fully described in Chapter 14, "Timers/Counters and Serial Interface." The I/O pins may be configured either for general-purpose I/O or for alternate functions (GPIF address and data; FIFO data; USART, timer, and interrupt signals; etc.).
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EZ-USB FX2 Technical Reference Manual Each port is associated with a pair of registers: • An OEx register (where x is A, B, C, D, or E), which sets the input/output direction of each of the 8 pins (0 = input, 1 = output). See Figure 13-2. • An IOx register (where x is A, B, C, D, or E). Values written to IOx appear on the pins which are configured as outputs; values read from IOx indicate the states of the 8 pins, regardless of input/output configuration. See Figure 13-3.
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OEA Port A Output Enable SFR 0xB2 b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/
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EZ-USB FX2 Technical Reference Manual IOA Port A (Bit-Addressable) SFR 0x80 b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4
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13.3 I/O Port Alternate Functions Each I/O pin may be configured for an alternate (i.e., non-general-purpose I/O) function. These alternate functions are selected through various configuration registers, as described in the following sections. The I/O-pin logic for alternate-function outputs is slightly different than for alternate-function inputs, as shown in Figures 13-4 (output) and 13-5 (input).
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EZ-USB FX2 Technical Reference Manual Alternate Function (Input) Alternate Function (Input) OEx Bit OEx Bit Write Write I/O Pin IOx Bit Read I/O Pin IOx Bit Read a) General-Purpose I/O Configuration b) Alternate-Function Configuration Figure 13-5. I/O-Pin Logic when Alternate Function is an INPUT Figure 13-5 shows an I/O pin whose alternate function is always an input. In Figure 13-5a, the I/O pin is configured for general-purpose I/O.
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13.3.1 Port A Alternate Functions Alternate functions for the Port A pins are selected by bits in three registers, as shown in Tables 13-1 and 13-2. Table 13-1.
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EZ-USB FX2 Technical Reference Manual 13.3.2 Port B and Port D Alternate Functions When IFCFG1 = 1, all eight Port B pins are configured for an alternate configuration (FIFO Data 7:0). If any of the FIFOs are set to 16-bit mode (via the WORDWIDE bits in the EPxFIFOCFG registers), all eight Port D pins are also configured for an alternate configuration (FIFO Data 15:8). See Tables 13-3, 13-4, and 13-5. If all WORDWIDE bits are cleared to 0 (i.e.
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13.3.3 Port C Alternate Functions Each Port C pin may be individually configured for an alternate function by setting a bit in the PORTCCFG register, as shown in Tables 13-6 and 13-7. Table 13-6. Register Bits Which Select Port C Alternate Functions PORTCCFG (0xE671) b7 b6 b5 b4 b3 b2 b1 b0 GPIFA7 GPIFA6 GPIFA5 GPIFA4 GPIFA3 GPIFA2 GPIFA1 GPIFA0 Table 13-7. Port C Alternate-Function Configuration Port C Pin Alternate Function Alternate Function is Selected By...
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EZ-USB FX2 Technical Reference Manual 13.3.4 Port E Alternate Functions Each Port E pin may be individually configured for an alternate function by setting a bit in the PORTECFG register. If the GSTATE bit in the IFCONFIG register is set to 1, the PE.2:0 pins are automatically configured as GPIF Status pins GSTATE[2:0], regardless of the PORTECFG.2:0 settings. In other words, GSTATE overrides PORTECFG.2:0. See Tables 13-8 and 13-9. Table 13-8.
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Table 13-10.
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EZ-USB FX2 Technical Reference Manual 13.4 I²C-Compatible Bus Controller The I ² C-compatible bus controller uses the SCL (Serial Clock) and SDA (Serial Data) pins, and performs two functions: • General-purpose interfacing to I² C peripherals • Boot loading from a serial EEPROM Pullup resistors are required on the SDA and SCL lines, even if nothing is connected to the I² C -compatible bus. Each line should be pulled up to Vcc through a 2.2K ohm resistor.
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start SDA SA3 SA2 SA1 SA0 DA2 DA1 DA0 R/W ACK D7 D6 SCL 1 2 3 4 5 6 7 8 9 10 11 Figure 13-7. Addressing an I²C Peripheral Each peripheral (slave) device on the I² C bus has a unique address. The first byte of an I ² C transaction contains the address of the desired peripheral. Figure 13-7 shows the format for this first byte, which is sometimes called a control byte.
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EZ-USB FX2 Technical Reference Manual I2CS I ²C-Compatible Bus Control and Status E678 b7 b6 b5 b4 b3 b2 b1 b0 START STOP LASTRD ID1 ID0 BERR ACK DONE R/W R/W R/W R R R R R 0 0 0 x x 0 0 0 I2DAT I²C-Compatible Bus Data E679 b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x I2CTL I² C-Compatible Bus Mode E67A b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 STOPE 400KHZ R R R R R R
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While the I²C-Compatible Bus controller is generating the “stop” condition, it ignores accesses to the I2CS and I2DAT registers. Firmware should therefore check the STOP Bit for zero before writing new data to I2CS or I2DAT. An interrupt request is available to signal that the STOP condition is complete. LASTRD The master reads data by floating the SDA line and issuing clock pulses on the SCL line; after every eight bits, it drives SDA low for one clock to indicate ACK.
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EZ-USB FX2 Technical Reference Manual dition is detected on the bus. BERR is automatically cleared when the firmware reads or writes the I2DAT register. Clearing the BERR bit (by accessing I2DAT) does not automatically re-enable the bus controller. Once a bus error occurs, the bus controller remains disabled until a STOP condition is detected. ID1, ID0 These bits are automatically set by the boot loader to indicate the Boot EEPROM’s addressing mode.
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11. Set STOP=1. 12. Read the last byte from I2DAT immediately (the next instruction) after setting the STOP bit. This retrieves the last data byte without initiating an extra read transaction (nine more SCL pulses) on the I ² C-compatible bus. * If INT3 is enabled, each “Wait for DONE=1” step can be interrupt-driven and handled by an interrupt service routine. See Chapter 4, "Interrupts" for more details. 13.
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EZ-USB FX2 Technical Reference Manual After determining whether a one- or two-byte-address EEPROM is attached, the FX2 reports its results in the ID1 and ID0 bits, as shown in Table 13-12. Table 13-12.
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Chapter 14 Timers/Counters and Serial Interface 14.1 Introduction The FX2’s timer/counters and serial interface are very similar to the standard 8051’s, with some differences and enhancements. This chapter provides technical information on configuring and using the timer/counters and serial interface. 14.2 Timers/Counters The FX2 includes three timer/counters (Timer 0, Timer 1, and Timer 2).
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EZ-USB FX2 Technical Reference Manual 14.2.1 803x/805x Compatibility The implementation of the timers/counters is similar to that of the Dallas Semiconductor DS80C320. Table 14-1 summarizes the differences in timer/counter implementation between the Intel 8051, the Dallas Semiconductor DS80C320, and the FX2. Table 14-1.
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14.2.2.1 Mode 0, 13-Bit Timer/Counter — Timer 0 and Timer 1 Mode 0 operation is illustrated in Figure 14-1. In mode 0, the timer is configured as a 13-bit counter that uses bits 0-4 of TL0 (or TL1) and all 8 bits of TH0 (or TH1). The timer enable bit (TR0/TR1) in the TCON SFR starts the timer. The C/T Bit selects the timer/counter clock source: either CLKOUT or the T0/T1 pins.
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EZ-USB FX2 Technical Reference Manual Table 14-2. TMOD Register — SFR 0x89 Bit Function TMOD.7 GATE1 - Timer 1 gate control. When GATE1 = 1, Timer 1 will clock only when INT1 = 1 and TR1 (TCON.6) = 1. When GATE1 = 0, Timer 1 will clock only when TR1 = 1, regardless of the state of INT1. TMOD.6 C/T1 - Counter/Timer select. When C/T1 = 0, Timer 1 is clocked by CLKOUT/4 or CLKOUT/ 12, depending on the state of T1M (CKCON.4). When C/T1 = 1, Timer 1 is clocked by highto-low transitions on the T1 pin.
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Table 14-3. TCON Register — SRF 0x88 Bit Function TCON.7 TF1 - Timer 1 overflow flag. Set to 1 when the Timer 1 count overflows; automatically cleared when the FX2 vectors to the interrupt service routine. TCON.6 TR1 - Timer 1 run control. 1 = Enable counting on Timer 1. TCON.5 TF0 - Timer 0 overflow flag. Set to 1 when the Timer 0 count overflows; automatically cleared when the FX2 vectors to the interrupt service routine. TCON.4 TR0 - Timer 0 run control. 1 = Enable counting on Timer 0. TCON.
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EZ-USB FX2 Technical Reference Manual Divide by 12 CLKOUT T0M (or T1M) 0 1 Divide by 4 C/ T 0 TL0 (or TL1) 0 7 RELOAD 1 CLK T0 (or T1) pin TR0 (or TR1) 0 TH0 (or TH1) 7 GATE TF0 (or TF1) INT0 (or INT1) pin INT To Serial Port (Timer 1 only) Figure 14-2. Timer 0/1 - Mode 2 14.2.2.4 Mode 3, Two 8-Bit Counters — Timer 0 Only In mode 3, Timer 0 operates as two 8-bit counters. Selecting mode 3 for Timer 1 simply stops Timer 1.
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T0M Divide by 12 0 CLKOUT 1 Divide by 4 0 C/ T CLK 7 TL0 0 1 T0 pin TR0 TF0 INT TF1 INT GATE INT0 pin 0 TH0 7 TR1 Figure 14-3. Timer 0 - Mode 3 14.2.3 Timer Rate Control By default, the FX2 timers increment every 12 CLKOUT cycles, just as in the standard 8051. Using this default rate allows existing application code with real-time dependencies, such as baud rate, to operate properly.
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EZ-USB FX2 Technical Reference Manual 14.2.4 Timer 2 Timer 2 runs only in 16-bit mode and offers several capabilities not available with Timers 0 and 1. The modes available for Timer 2 are: • 16-bit timer/counter • 16-bit timer with capture • 16-bit timer/counter with auto-reload • Baud rate generator The SFRs associated with Timer 2 are: • T2CON (SFR 0xC8) — Timer/Counter 2 Control register, (see Table 14-5).
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Table 14-5. T2CON Register — SFR 0xC8 Bit Function T2CON.7 TF2 - Timer 2 overflow flag. Hardware will set TF2 when the Timer 2 overflows from 0xFFFF. TF2 must be cleared to 0 by the software. TF2 will only be set to a 1 if RCLK and TCLK are both cleared to 0. Writing a 1 to TF2 forces a Timer 2 interrupt if enabled. T2CON.6 EXF2 - Timer 2 external flag. Hardware will set EXF2 when a reload or capture is caused by a high-to-low transition on the T2EX pin, and EXEN2 is set.
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EZ-USB FX2 Technical Reference Manual 14.2.5 Timer 2 — 16-Bit Timer/Counter Mode Figure 14-4 illustrates how Timer 2 operates in timer/counter mode with the optional capture feature. The C/T2 Bit determines whether the 16-bit counter counts CLKOUT cycles (divided by 4 or 12), or high-to-low transitions on the T2 pin. The TR2 Bit enables the counter. When the count increments from 0xFFFF, the TF2 flag is set and the T2OUT pin goes high for one CLKOUT cycle. 14.2.5.
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Divide by 12 CLKOUT CP/RL2 = 0 T2M 0 1 Divide by 4 0 C/ T2 CLK 7 8 0 TL2 1 15 TH2 T2 pin RCAP2L TR2 0 RCAP2H 78 15 TF2 EXEN2 INT EXF2 T2EX pin Figure 14-5. Timer 2 - Timer/Counter with Auto Reload 14.2.7 Timer 2 — Baud Rate Generator Mode Setting either RCLK or TCLK to 1 configures Timer 2 to generate baud rates for Serial Port 0 in serial mode 1 or 3. Figure 14-6 is the functional diagram for the Timer 2 baud rate generator mode.
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EZ-USB FX2 Technical Reference Manual CLKOUT Divide by 2 0 TIMER 1 OVERFLOW C/ T2 CLK 1 Divide by 2 T2 pin TR2 SMOD0 0 7 8 0 TL2 1 RCLK 15 TH2 0 1 RX CLOCK Divide by 16 TCLK RCAP2L 0 RCAP2H 7 8 15 1 EXEN2 0 Divide by 16 TX CLOCK EXF2 T2EX pin TIMER 2 INTERRUPT Figure 14-6. Timer 2 - Baud Rate Generator Mode 14.3 Serial Interface The FX2 provides two serial ports.
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Table 14-7.
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EZ-USB FX2 Technical Reference Manual 14.3.2 High-Speed Baud Rate Generator The FX2 incorporates a high-speed baud rate generator which can provide 115.2K and 230.4K baud rates for either or both serial ports, regardless of the FX2’s internal clock frequency (12, 24, or 48 MHz). The high-speed baud rate generator is enabled for Serial Port 0 by setting UART230.0 to 1; it’s enabled for Serial Port 1 by setting UART230.1 to 1. When enabled, the high-speed baud rate generator defaults to 115.2K baud.
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14.3.3 Mode 0 Serial mode 0 provides synchronous, half-duplex serial communication. For Serial Port 0, serial data output occurs on the RXD0OUT pin, serial data is received on the RXD0 pin, and the TXD0 pin provides the shift clock for both transmit and receive. For Serial Port 1, the corresponding pins are RXD1OUT, RXD1, and TXD1. The serial mode 0 baud rate is either CLKOUT/12 or CLKOUT/4, depending on the state of the SM2_0 bit (or SM2_1 for Serial Port 1).
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EZ-USB FX2 Technical Reference Manual Table 14-11. SCON0 Register — SFR 98h Bit Function SCON0.7 SM0_0 - Serial Port 0 mode bit 0. SCON0.6 SM1_0 - Serial Port 0 mode bit 1, decoded as: SM0_0 SM1_0 Mode SCON0.5 0 0 0 0 1 1 1 0 2 1 1 3 SM2_0 - Multiprocessor communication enable. In modes 2 and 3, this bit enables the multiprocessor communication feature. If SM2_0 = 1 in mode 2 or 3, then RI_0 will not be activated if the received 9th bit is 0.
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Table 14-14. SCON1 Register — SFR C0h Bit Function SCON1.7 SM0_1 - Serial Port 1 mode bit 0. SCON1.6 SM1_1 - Serial Port 1 mode bit 1, decoded as: SM0_1 SM1_1 Mode SCON1.5 0 0 0 0 1 1 1 0 2 1 1 3 SM2_1 - Multiprocessor communication enable. In modes 2 and 3, this bit enables the multiprocessor communication feature. If SM2_1 = 1 in mode 2 or 3, then RI_1 will not be activated if the received 9th bit is 0. If SM2_1=1 in mode 1, then RI_1 will only be activated if a valid stop is received.
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EZ-USB FX2 Technical Reference Manual CLKOUT D0 RXD0 D1 D2 D3 D4 D5 D6 D7 RXD0OUT TXD0 TI RI Figure 14-7. Serial Port Mode 0 Receive Timing - Low Speed Operation CLKOUT RXD0 D0 D1 D2 D3 D4 D5 D6 D7 RXD0OUT TXD0 TI RI Figure 14-8. Serial Port Mode 0 Receive Timing - High Speed Operation At both low and high speed in Mode 0, data on RXD0 is sampled two CLKOUT cycles before the rising clock edge on TXD0. Page 14-18 EZ-USB FX2 Technical Reference Manual v2.
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CLKOUT RXD0 RXD0OUT D0 D1 D2 D3 D4 D5 D6 D7 TXD0 TI RI Figure 14-9. Serial Port Mode 0 Transmit Timing - Low Speed Operation CLKOUT RXD0 RXD0OUT D0 D1 D2 D3 D4 D5 D6 D7 TXD0 TI RI Figure 14-10. Serial Port Mode 0 Transmit Timing - High Speed Operation Chapter 14.
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EZ-USB FX2 Technical Reference Manual 14.3.4 Mode 1 Mode 1 provides standard asynchronous, full-duplex communication, using a total of 10 bits: 1 start bit, 8 data bits, and 1 stop bit. For receive operations, the stop bit is stored in RB8_0 (or RB8_1). Data bits are received and transmitted LSB first. Mode 1 operation is identical to that of the standard 8051 when Timer 1 uses CLKOUT/12, (T1M=0, the default). 14.3.4.1 Mode 1 Baud Rate The mode 1 baud rate is a function of timer overflow.
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To derive the required TH1 value from a known baud rate when T1M=1, use the equation: TH1 = SMODx 2 x CLKOUT 256 - 128 x Baud Rate Very low serial port baud rates may be achieved with Timer 1 by enabling the Timer 1 interrupt, configuring Timer 1 to mode 1, and using the Timer 1 interrupt to initiate a 16-bit software reload. Table 14-15 lists sample reload values for a variety of common serial port baud rates, using Timer 1 operating in mode 2 (TMOD.
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EZ-USB FX2 Technical Reference Manual To derive the required RCAP2H and RCAP2L values from a known baud rate, use the equation: RCAP2H:L = 65536 - CLKOUT 32 × Baud Rate When either RCLK or TCLK is set, the TF2 flag is not set on a Timer 2 rollover and the T2EX reload trigger is disabled. Table 14-16 lists sample RCAP2H:L reload values for a variety of common serial baud rates. Table 14-16.
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of a start bit is detected, the divide-by-16 counter used to generate the receive clock is reset to align the counter rollover to the bit boundaries. For noise rejection, the serial port establishes the content of each received bit by a majority decision of 3 consecutive samples in the middle of each bit time.
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EZ-USB FX2 Technical Reference Manual RX CLK RXD0 START D0 D1 D2 D3 D4 D5 D6 D7 STOP Bit detector sampling SHIFT RXD0OUT TXD0 TI_0 RI_0 Figure 14-12. Serial Port 0 Mode 1 Receive Timing 14.3.6 Mode 2 Mode 2 provides asynchronous, full-duplex communication, using a total of 11 bits: 1 start bit, 8 data bits, a programmable 9th bit, and 1 stop bit. The data bits are transmitted and received LSB first. For transmission, the 9th bit is determined by the value in TB8_0 (or TB8_1).
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14.3.6.2 Mode 2 Receive Figure 14-14 illustrates the mode 2 receive timing. Reception begins at the falling edge of a start bit received on the RXD0 (or RXD1) pin, when enabled by the REN_0 (or REN_1) Bit. For this purpose, the RXD0 (or RXD1) pin is sampled 16 times per bit for any baud rate. When a falling edge of a start bit is detected, the divide-by-16 counter used to generate the receive clock is reset to align the counter rollover to the bit boundaries.
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EZ-USB FX2 Technical Reference Manual RX CLK RXD0 START D0 D1 D2 D3 D4 D5 D6 D7 RB8 STOP Bit detector sampling SHIFT RXD0OUT TXD0 TI_0 RI_0 Figure 14-14. Serial Port 0 Mode 2 Receive Timing 14.3.7 Mode 3 Mode 3 provides asynchronous, full-duplex communication, using a total of 11 bits: 1 start bit, 8 data bits, a programmable 9th bit, and 1 stop bit. The data bits are transmitted and received LSB first. The mode 3 transmit and operations are identical to mode 2.
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Write to SBUF0 TX CLK SHIFT TXD0 START D0 D1 D2 D3 D4 D5 D6 D7 TB8 STOP RXD0 RXD0OUT TI_0 RI_0 Figure 14-15. Serial Port 0 Mode 3 Transmit Timing RX CLK RXD0 S TA R T D0 D1 D2 D3 D4 D5 D6 D7 RB8 S TO P Bit detector sampling SHIFT RXD0OUT TXD0 TI_0 RI_0 Figure 14-16. Serial Port 0 Mode 3 Receive Timing Chapter 14.
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EZ-USB FX2 Technical Reference Manual Page 14-28 EZ-USB FX2 Technical Reference Manual v2.
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Chapter 15 Registers 15.1 Introduction This section describes the EZ-USB FX2 registers in the order they appear in the EZ-USB FX2 memory map, see Figure 5-4. The registers are named according to the following conventions. Most registers deal with endpoints. The general register format is DDDnFFF, where: DDD is endpoint direction, IN or OUT with respect to the USB host. n is the endpoint number, where: • FFF “ISO” indicates isochronous endpoints as a group.
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EZ-USB FX2 Technical Reference Manual 15.1.2 Other Conventions USB Indicates a global (not endpoint-specific) USB function. ADDR Is an address. VAL Means valid. FRAME Is a frame count. PTR Is an address pointer.
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15.2 Special Function Registers (SFR) FX2 implements many control registers as SFRs (Special Function Registers). These SFRs are shown in Table 15-1. Bold type indicates SFRs which are not in the standard 8051, but are included in the FX2. Table 15-1.
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EZ-USB FX2 Technical Reference Manual 15.3 About SFRS Because the SFRs are directly-addressable internal registers, firmware can access them quickly, without the overhead of loading the data pointer and performing a MOVX instruction. For example, the firmware reads the FX2 Port B pins using a single instruction, as shown in Figure 15-2. mov a,IOB Figure 15-2. Single Instruction to Read Port B Similarly, firmware writes the value 0x55 to Port C using only one MOV instruction, as shown in Figure 15-3.
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IOB Port B (bit addressable) SFR 0x90 b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x AUTOPTRH1 Autopointer 1 Address HIGH SFR 0x9A b7 b6 b5 b4 b3 b2 b1 b0 A15 A14 A13 A12 A11 A10 A9 A8 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 AUTOPTRL1 Autopointer 1 Address LOW SFR 0x9B b7 b6 b5 b4 b3 b2 b1 b0 A7 A6 A5 A4 A3 A2 A1 A0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0
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EZ-USB FX2 Technical Reference Manual AUTOPTRL2 Autopointer 2 Address LOW SFR 0x9E b7 b6 b5 b4 b3 b2 b1 b0 A7 A6 A5 A4 A3 A2 A1 A0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 IOC Port C (bit addressable) SFR 0xA0 b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x INT2CLR Interrupt 2 Clear SFR 0xA1 b7 b6 b5 b4 b3 b2 b1 b0 x x x x x x x x W W W W W W W W x x x x
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The firmware can do this either by accessing the EP2FIFOIRQ register (at 0xE651) and writing a 1 to bit 1, or simply by writing any value to INT4CLR. The first method requires the use of the data pointer, which must be saved and restored along with the accumulator in an ISR. The second method is much faster and does not require saving the data pointer, so it is preferred.
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EZ-USB FX2 Technical Reference Manual EP24FIFOFLGS Endpoint(s) 2, 4 Slave FIFO Status Flags SFR 0xAB b7 b6 b5 b4 b3 b2 b1 b0 0 EP4PF EP4EF EP4FF 0 EP2PF EP2EF EP2FF R R R R R R R R 0 0 1 0 0 0 1 0 EP68FIFOFLGS Endpoint(s) 6, 8 Slave FIFO Status Flags SFR 0xAC b7 b6 b5 b4 b3 b2 b1 b0 0 EP8PF EP8EF EP8FF 0 EP6PF EP6EF EP6FF R R R R R R R R 0 1 1 0 0 1 1 0 AUTOPTRSETUP Autopointer(s) 1 & 2 Setup SFR 0xAF b7 b6 b5 b4 b3 b2 b1 b0 0
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IOD Port D (bit addressable) SFR 0xB0 b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x FX2 I/O ports PORTA-PORTD appear as bit-addressable SFRS. Reading a register or bit returns the logic level of the port pin that’s two CLKOUT-clocks old. Writing a register bit writes the port latch. Whether or not the port latch value appears on the I/O pin depends on the state of the pin’s OE (Output Enable) bit.
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EZ-USB FX2 Technical Reference Manual OEA Port A Output Enable SFR 0xB2 b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 OEB Port B Output Enable SFR 0xB3 b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 OEC Port C Output Enable SFR 0xB4 b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W 0
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OED Port D Output Enable SFR 0xB5 b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 OEE Port E Output Enable SFR 0xB6 b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 The bits in 0EA - 0EE turn on the output buffers for the five IO Ports PORTA-PORTE. Setting a bit to 1 turns on the output buffer, setting it to 0 turns the buffer off.
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EZ-USB FX2 Technical Reference Manual GPIFSGLDATH GPIF Data HIGH (16-bit mode only) SFR 0xBD b7 b6 b5 b4 b3 b2 b1 b0 D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x GPIFSGLDATLX GPIF Data LOW w/Trigger SFR 0xBE b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x GPIFSGLDATLNOX GPIF Data LOW w/No Trigger SFR 0xBF b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3
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15.4 GPIF Waveform Memories 15.4.1 GPIF Waveform Descriptor Data WAVEDATA GPIF Waveform Descriptor 0, 1, 2, 3 Data E400-E47F* b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x *Accessible only when IFCFG1:0 = 10. Figure 15-6. GPIF Waveform Descriptor Data The four GPIF waveform descriptor tables are stored in this space. See Chapter 10 "General Programmable Interface (GPIF)" for details. 15.
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EZ-USB FX2 Technical Reference Manual The RD and WR strobes are asserted for two CLKOUT cycles; the WR strobe asserts two CLKOUT cycles after the PORTC pins are updated. If a design uses the 128-pin FX2 and connects off-chip memory to the address and data buses, this bit should be set to zero. This is because the RD and WR pins are also the standard strobes used to read and write off-chip memory, so normal reads/writes to I/O Port C would disrupt normal accesses to that memory.
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Bit 7 IFCLKSRC FIFO/GPIF Clock Source This bit selects the clock source for both the FIFOS and GPIF. If IFCLKSRC=0, the external clock on the IFCLK pin is selected. If IFCLKSRC=1 (default), an internal 30- or 48-MHz (default) clock is used. Bit 6 3048MHZ Internal FIFO/GPIF Clock Frequency Table 15-5. Internal FIFO/GPIF Clock Frequency 3048MHZ FIFO & GPIF Clock 0 30 MHz 1 48 MHz(default) This bit selects the internal FIFO & GPIF clock frequency.
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EZ-USB FX2 Technical Reference Manual Bit 3 ASYNC FIFO/GPIF Asynchronous Mode When ASYNC=0, the FIFO/GPIF operate synchronously: a clock is supplied either internally or externally on the IFCLK pin; the FIFO control signals function as read and write enable signals for the clock signal. When ASYNC=1, the FIFO/GPIF operate asynchronously: no clock signal input to IFCLK is required; the FIFO control signals function directly as read and write strobes.
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Table 15-8.
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EZ-USB FX2 Technical Reference Manual 15.5.3 Slave FIFO FLAGA-FLAGD Pin Configuration PINFLAGSAB Slave FIFO FLAGA and FLAGB Pin Configuration see Section 15.14 E602 b7 b6 b5 b4 b3 b2 b1 b0 FLAGB3 FLAGB2 FLAGB1 FLAGB0 FLAGA3 FLAGA2 FLAGA1 FLAGA0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 PINFLAGSCD Slave FIFO FLAGC and FLAGD Pin Configuration see Section 15.
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Table 15-9. FIFO Flag Pin Functions FLAGx3 FLAGx2 FLAGx1 FLAGx0 Pin Function 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 EP2 PF 0 1 0 1 EP4 PF 0 1 1 0 EP6 PF 0 1 1 1 EP8 PF 1 0 0 0 EP2 EF 1 0 0 1 EP4 EF 1 0 1 0 EP6 EF 1 0 1 1 EP8 EF 1 1 0 0 EP2 FF 1 1 0 1 EP4 FF 1 1 1 0 EP6 FF 1 1 1 1 EP8 FF FLAGA=PF, FLAGB=FF, FLAGC=EF, FLAGD=EP2PF (Actual FIFO is selected by FIFOADR[0,1] pins) Reserved NOTE: FLAGD defaults to EP2PF (fixed flag).
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EZ-USB FX2 Technical Reference Manual 15.5.4 FIFO Reset FIFORESET Restore FIFOs to Default State E604 see Section 15.14 b7 b6 b5 b4 b3 b2 b1 b0 NAKALL 0 0 0 EP3 EP2 EP1 EP0 W W W W W W W W x x x x x x x x Figure 15-11. Restore FIFOs to Reset State Write 0x80 to this register to NAK all transfers from the host, then write 0x02, 0x04, 0x06, or 0x08 to reset an individual FIFO (i.e.
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Bit 2 BPPULSE Breakpoint Pulse Mode Set this bit to “1” to pulse the BREAK bit (and BKPT pin) high for 8 CLKOUT cycles when the 8051 address bus matches the address held in the breakpoint address registers. When this bit is set to “0”, the BREAK bit (and BKPT pin) remains high until it is cleared by firmware. Bit 1 BPEN Breakpoint Enable If this bit is “1”, a BREAK signal is generated whenever the 16-bit address lines match the value in the Breakpoint Address Registers (BPADDRH:L).
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EZ-USB FX2 Technical Reference Manual 15.5.6 230 Kbaud Clock (T0, T1, T2) UART230 230 KBaud clock for T1 E608 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 230UART1 230UART0 R R R R R R R/W R/W 0 0 0 0 0 0 0 0 Figure 15-15. 230 Kbaud Internally Generated Reference Clock Bit 1- 0 230UARTx Set 230 KBaud Operation Setting these bits to 1 overrides the timer inputs to the USARTs, and USART0 and USART1 will use the 230 KBaud clock rate.
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Bit 3 SLRD FIFO Read Polarity This bit selects the polarity of the SLRD FIFO input pin. 0 selects the polarity shown in the data sheet (active low). 1 selects active high. Bit 2 SLWR FIFO Write Polarity This bit selects the polarity of the SLWR FIFO input pin. 0 selects the polarity shown in the data sheet (active low). 1 selects active high. Bit 1 EF Empty Flag Polarity This bit selects the polarity of the SLWR FIFO output pin. 0 selects the polarity shown in the data sheet (active low).
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EZ-USB FX2 Technical Reference Manual 15.5.9 Chip Revision Control REVCTL Chip Revision Control E60B See Section 15.14 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 DYN_OUT ENH_PKT R R R R R R R/W R/W 0 0 0 0 0 0 0 0 Figure 15-18. Chip Revision Control DYN_OUT and ENH_PKT default to 0 on POR. Cypress highly recommends setting both bits to 1.
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15.5.10 GPIF Hold Time GPIFHOLDTIME E60C b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 HOLDTIME[1:0] R R R R R R RW RW 0 0 0 0 0 0 0 0 For any transaction where the GPIF writes data onto FD[15:0], this register determines how long the data is held. Valid choices are 0, ½ or 1 IFCLK cycle. This register applies to any data written by the GPIF to FD[15:0], whether through a flow state or not.
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EZ-USB FX2 Technical Reference Manual 15.6 Endpoint Configuration 15.6.1 Endpoint 1-OUT/Endpoint 1-IN Configurations EP1OUTCFG EP1INCFG Endpoint 1-OUT Configuration Endpoint 1-IN Configuration E610 E611 b7 b6 b5 b4 b3 b2 b1 b0 VALID 0 TYPE1 TYPE0 0 0 0 0 R/W R R/W R/W R R R R 1 0 1 0 0 0 0 0 Figure 15-19. Endpoint 1-OUT/Endpoint 1-IN Configurations Bit 7 VALID Activate an Endpoint Set VALID=1 to activate an endpoint, and VALID=0 to de-activate it.
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15.6.2 Endpoint 2, 4, 6 and 8 Configuration EP2CFG Endpoint 2 Configuration E612 b7 b6 b5 b4 b3 b2 b1 b0 VALID DIR TYPE1 TYPE0 SIZE 0 BUF1 BUF0 R/W R/W R/W R/W R/W R R/W R/W 1 0 1 0 0 0 1 0 Figure 15-20. Endpoint 2 Configuration EP4CFG Endpoint 4 Configuration E613 b7 b6 b5 b4 b3 b2 b1 b0 VALID DIR TYPE1 TYPE0 0 0 0 0 R/W R/W R/W R/W R R R R 1 0 1 0 0 0 0 0 Figure 15-21.
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EZ-USB FX2 Technical Reference Manual These registers configure the large, data-handling FX2 endpoints. Bit 7 VALID Activate an Endpoint Set VALID=1 to activate an endpoint, and VALID=0 to de-activate it. All FX2 endpoints default to valid. An endpoint whose VALID bit is 0 does not respond to any USB traffic. Bit 6 DIR Sets Endpoint Direction 0 = OUT, 1 = IN Bit 5-4 TYPE Defines the Endpoint Type These bits define the endpoint type, as shown in the table below.
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15.6.3 Endpoint 2, 4, 6 and 8/Slave FIFO Configuration EP2FIFOCFG Endpoint 2/Slave FIFO Configuration E618 Endpoint 4/Slave FIFO Configuration E619 Endpoint 6/Slave FIFO Configuration E61A Endpoint 8/Slave FIFO Configuration E61B see Section 15.14 EP4FIFOCFG see Section 15.14 EP6FIFOCFG see Section 15.14 EP8FIFOCFG see Section 15.14 b7 b6 b5 b4 b3 b2 b1 b0 0 INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0 WORDWIDE R R/W R/W R/W R/W R/W R R/W 0 0 0 0 0 1 0 1 Figure 15-24.
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EZ-USB FX2 Technical Reference Manual When AUTOOUT=0, as soon as a buffer fills with USB data, an endpoint interrupt is asserted. The connection of the buffer to the endpoint FIFO is under control of the firmware, rather than automatically being connected. Using this method, the firmware can inspect the data in OUT packets, and based on what it finds, choose to include that packet in the endpoint FIFO or not. The firmware can even modify the packet data, and then commit it to the endpoint FIFO.
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15.6.4 Endpoint 2, 4, 6, 8 AUTOIN Packet Length (High/Low) EP2AUTOINLENH see Section 15.14 EP6AUTOINLENH see Section 15.14 Endpoint 2 AUTOIN Packet Length HIGH Endpoint 6 AUTOIN Packet Length HIGH E620 E624 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 PL10 PL9 PL8 R R R R R R/W R/W R/W 0 0 0 0 0 0 1 0 Figure 15-25. Endpoint 2 and 6 AUTOIN Packet Length High Bit 2-0 PL10:8 Packet Length High High three bits of Packet Length. EP4AUTOINLENH see Section 15.
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EZ-USB FX2 Technical Reference Manual EP2AUTOINLENL see Section 15.14 EP4AUTOINLENL see Section 15.14 EP6AUTOINLENL see Section 15.14 EP8AUTOINLENL see Section 15.14 Endpoint 2 AUTOIN Packet Length LOW Endpoint 4 AUTOIN Packet Length LOW Endpoint 6 AUTOIN Packet Length LOW Endpoint 8 AUTOIN Packet Length LOW E621 E623 E625 E627 b7 b6 b5 b4 b3 b2 b1 b0 PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Figure 15-27.
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15.6.5 Endpoint 2, 4, 6, 8 /Slave FIFO Programmable-Level Flag (High/Low) EP2FIFOPFH Endpoint 2/Slave FIFO Programmable-Level Flag HIGH [HIGH SPEED (480 Mbit/Sec) Mode and FULL-SPEED (12 Mbit/Sec) Iso Mode] see Section 15.
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EZ-USB FX2 Technical Reference Manual EP6FIFOPFH Endpoint 6/Slave FIFO Programmable-Level Flag HIGH [HIGH SPEED (480 Mbit/Sec) Mode and FULL-SPEED (12 Mbit/Sec) Iso Mode] see Section 15.14 b7 b6 DECIS PKTSTAT R/W R/W R/W R/W 0 0 0 0 EP6FIFOPFH b5 b4 b3 b2 b1 b0 0 PFC9 PFC8 R/W R/W R/W R/W 1 0 0 0 IN: PKTS[2] IN: PKTS[1] IN: PKTS[0] OUT:PFC12 OUT:PFC11 OUT:PFC10 Endpoint 6/Slave FIFO Programmable-Level Flag HIGH [FULL SPEED (12 Mbit/Sec) Non-Iso Mode] see Section 15.
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By default, FLAGA is the Programmable-Level Flag (PF) for the endpoint currently pointed to by the FIFOADR[1:0] pins. For EP2 and EP4, the default endpoint configuration is BULK, OUT, 512, 2x, and the PF pin asserts when the entire FIFO has greater than/equal to 512 bytes. For EP6 and EP8, the default endpoint configuration is BULK, IN, 512, 2x, and the PF pin asserts when the entire FIFO has less than/equal to 512 bytes.
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EZ-USB FX2 Technical Reference Manual EP4FIFOPFH Endpoint 4/Slave FIFO Programmable-Level Flag HIGH [HIGH SPEED (480 Mbit/Sec) Mode and FULL-SPEED (12 Mbit/Sec) Iso Mode] see Section 15.14 b7 b6 b5 DECIS PKTSTAT 0 R/W R/W R R/W 1 0 0 0 EP4FIFOPFH b4 b3 b2 b1 b0 0 0 PFC8 R/W R R R/W 1 0 0 0 IN: PKTS[1] IN: PKTS[0] OUT:PFC10 OUT:PFC9 Endpoint 4/Slave FIFO Programmable-Level Flag HIGH [FULL SPEED (12 Mbit/Sec) Non-Iso Mode] see Section 15.
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EP8FIFOPFH Endpoint 8/Slave FIFO Programmable-Level Flag HIGH [HIGH SPEED (480 Mbit/Sec) Mode and FULL-SPEED (12 Mbit/Sec) Iso Mode] see Section 15.14 b7 b6 b5 b4 DECIS PKTSTAT 0 R/W R/W R R/W 0 0 0 0 b3 E636 b2 b1 b0 0 0 PFC8 R/W R R R/W 1 0 0 0 IN: PKTS[1] IN: PKTS[0] OUT:PFC10 OUT:PFC9 . EP8FIFOPFH Endpoint 8/Slave FIFO Programmable-Level Flag HIGH [FULL SPEED (12 Mbit/Sec) Non-Iso Mode] see Section 15.
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EZ-USB FX2 Technical Reference Manual EP2FIFOPFL Endpoint 2/Slave FIFO Prog. Flag LOW E631 Endpoint 4/Slave FIFO Prog. Flag LOW E633 Endpoint 6/Slave FIFO Prog. Flag LOW E635 Endpoint 8/Slave FIFO Prog. Flag LOW [HIGH SPEED (480 Mbit/Sec) Mode and FULL-SPEED (12 Mbit/Sec) Iso Mode] E637 see Section 15.14 EP4FIFOPFL see Section 15.14 EP6FIFOPFL see Section 15.14 EP8FIFOPFL see Section 15.
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15.6.5.1 IN Endpoints For IN endpoints, the Trigger registers can apply to either the full FIFO, comprising multiple packets, or only to the current packet being filled. The PKTSTAT bit controls this choice: Table 15-14. Interpretation of PF for IN Endpoints PKTSTAT PF applies to: EPxFIFOPFH:L format 0 PKTS + Current packet bytes PKTS[ ] PBC[ ] 1 Current packet bytes only PBC[ ] Example 1: The following is an example of how you might use the first case. Assume a Bulk IN transfer over Endpoint 2.
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EZ-USB FX2 Technical Reference Manual Example 2: If you want the PF to inform the outside interface (the logic that is filling the IN FIFO) whenever the current packet is 75% full, set PKTSTAT=1, and load a packet byte count of 75: EP2FIFOPFH = 11xxx000 EP2FIFOPFHL = 75 Setting PKTSTAT=1 causes the PF decision to be based on the byte count alone, ignoring the packet count. This mode is valuable for double-buffered endpoints, where only the byte count of the currently-filling packet is important. 15.6.5.
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15.6.6 Endpoint 2, 4, 6, 8 ISO IN Packets per Frame EP2ISOINPKTS EP4ISOINPKTS EP6ISOINPKTS EP8ISOINPKTS Endpoint 2 (if ISO) IN Packets Per Frame Endpoint 4 (if ISO) IN Packets Per Frame Endpoint 6 (if ISO) IN Packets Per Frame Endpoint 8 (if ISO) IN Packets Per Frame E640 E641 E642 E643 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 INPPF1 INPPF0 R R R R R R R/W R/W 0 0 0 0 0 0 0 1 Figure 15-34.
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EZ-USB FX2 Technical Reference Manual Bit 7 SKIP Skip Packet When ENH_PKT (REVCTL.0) is set to 1, setting this bit to a “1“ will skip the IN packet. Clearing this bit to 0 automatically ‘dispatches’ an IN buffer. Bit 3-0 EP3:0 Endpoint Number Duplicates the function of the PKTEND pin. This feature is used only for IN transfers.
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15.7 Interrupts 15.7.1 Endpoint 2, 4, 6, 8 Slave FIFO Flag Interrupt Enable/Request EP2FIFOIE EP2 Slave FIFO Flag Interrupt Enable (INT4) E650 EP4 Slave FIFO Flag Interrupt Enable (INT4) E652 EP6 Slave FIFO Flag Interrupt Enable (INT4) E654 EP8 Slave FIFO Flag Interrupt Enable (INT4) E656 see Section 15.14 EP4FIFOIE see Section 15.14 EP6FIFOIE see Section 15.14 EP8FIFOIE see Section 15.
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EZ-USB FX2 Technical Reference Manual Bit 1 EF Empty Flag When this bit is '1', the empty flag interrupt is enabled on INT4. When this bit is '0' the empty flag interrupt is disabled. Bit 0 FF Full Flag When this bit is '1', the full flag interrupt is enabled on INT4. When this bit is '0' the full flag interrupt is disabled.
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Bit 0 FF Full Flag FX2 sets FF to 1 to indicate a “full flag” interrupt request. The interrupt source is available in the interrupt vector register IVEC4. Do not clear an IRQ Bit by reading an IRQ Register, ORing its contents with a bit mask, and writing back the IRQ Register. This will clear ALL pending interrupts. Instead, simply write the bit mask value (with a “1” in the bit position of the IRQ you want to clear) directly to the IRQ Register. 15.7.
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EZ-USB FX2 Technical Reference Manual Do not clear an IRQ bit by reading an IRQ Register, ORing its contents with a bit mask, and writing back the IRQ Register. This will clear ALL pending interrupts. Instead, simply write the bit mask value (with a “1” in the bit position of the IRQ you want to clear) directly to the IRQ Register. 15.7.
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Bit 0 IBN IBN INT Enable/Request This bit is automatically set when any of the IN bulk endpoints responds to an IN token with a NAK. This interrupt occurs when the host sends an IN token to a bulk IN endpoint which has not yet been armed. Individual enables and requests (per endpoint) are controlled by the IBNIE and IBNIRQ Registers. Write a “1” to this bit to clear the interrupt request. The IBN INT only fires on a 0-to-1 transition of an “OR” condition of all IBN sources that are enabled.
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EZ-USB FX2 Technical Reference Manual Bit 5 HSGRANT Grant High Speed Access The FX2 SIE sets this bit when it has been granted high speed (480 Mbits/sec) access to USB. Bit 4 URES USB Reset Interrupt Request The USB signals a bus reset by driving both D+ and D- low for at least 10 milliseconds. When the USB core detects the onset of USB bus reset, it activates the URES Interrupt Request. The USB core sets this bit to “1” when it detects a USB bus reset.
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15.7.5 Endpoint Interrupt Enable/Request EPIE Endpoint Interrupt Enables (INT2) E65E b7 b6 b5 b4 b3 b2 b1 b0 EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Figure 15-45. Endpoint Interrupt Enables EPIRQ Endpoint Interrupt Requests (INT2) E65F b7 b6 b5 b4 b3 b2 b1 b0 EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Figure 15-46.
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EZ-USB FX2 Technical Reference Manual 15.7.6 GPIF Interrupt Enable/Request GPIFIE GPIF Interrupt Enable (INT4) E660 see Section 15.14 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 GPIFWF GPIFDONE R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Figure 15-47. GPIF Interrupt Enable GPIFIRQ GPIF Interrupt Request (INT4) E661 see Section 15.
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15.7.7 USB Error Interrupt Enable/Request USBERRIE USB Error Interrupt Enables (INT2) E662 b7 b6 b5 b4 b3 b2 b1 b0 ISOEP8 ISOEP6 ISOEP4 ISOEP2 0 0 0 ERRLIMIT R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Figure 15-49. USB Error Interrupt Enables USBERRIRQ USB Error Interrupt Request (INT2) E663 b7 b6 b5 b4 b3 b2 b1 b0 ISOEP8 ISOEP6 ISOEP4 ISOEP2 0 0 0 ERRLIMIT R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Figure 15-50.
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EZ-USB FX2 Technical Reference Manual 15.7.8 USB Error Counter Limit ERRCNTLIM USB Error Counter and Limit E664 b7 b6 b5 b4 b3 b2 b1 b0 EC3 EC2 EC1 EC0 LIMIT3 LIMIT2 LIMIT1 LIMIT0 R R R R R/W R/W R/W R/W x x x x 0 1 0 0 Figure 15-51. USB Error Counter and Limit Bit 7-4 EC3:0 USB Error Count Error count has a maximum value of 15. Bit 3-0 LIMIT3:0 Error Count Limit USB bus error count and limit.
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15.7.10 INT 2 (USB) Autovector INT2IVEC INTERRUPT 2 (USB) Autovector E666 b7 b6 b5 b4 b3 b2 b1 b0 0 I2V4 I2V3 I2V2 I2V1 I2V0 0 0 R R R R R R R R 0 0 0 0 0 0 0 0 Figure 15-53. INT 2 (USB) Autovector Bit 6-2 I2V4:0 INT 2 Autovector To save the code and processing time required to sort out which USB interrupt occurred, the USB core provides a second level of interrupt vectoring, called Autovectoring.
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EZ-USB FX2 Technical Reference Manual I4V indicates the source of an interrupt from the USB Core. When the USB core generates an INT4 (FIFO/GPIF) Interrupt Request, it updates INT4IVEC to indicate the source of the interrupt. The interrupt sources are encoded on I2V3:0. 15.7.12 INT 2 and INT 4 Setup INTSETUP INT 2 & INT 4 Setup E668 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 AV2EN 0 INT4SRC AV4EN R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Figure 15-55.
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15.8 Input/Output Registers 15.8.1 I/O PORTA Alternate Configuration PORTACFG I/O PORTA Alternate Configuration E670 b7 b6 b5 b4 b3 b2 b1 b0 FLAGD SLCS 0 0 0 0 INT1 INT0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Figure 15-56. I/O PORTA Alternate Configuration Note: Bit 3 is the WU2EN bit in the Wakeup register. The PORTxCFG register selects alternate functions for the PORTx pins.
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EZ-USB FX2 Technical Reference Manual 15.8.2 I/O PORTC Alternate Configuration PORTCCFG I/O PORTC Alternate Configuration E671 b7 b6 b5 b4 b3 b2 b1 b0 GPIFA7 GPIFA6 GPIFA5 GPIFA4 GPIFA3 GPIFA2 GPIFA1 GPIFA0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Figure 15-57. I/O PORTC Alternate Configuration Bit 7-0 GPIFA7:0 Enable GPIF Address Pins Set these pins to “1” to configure this port to output the lower address of enabled GPIF address pins.
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Bit 5 INT6 INT6 Interrupt Request Setting this bit to '1' configures this Port E pin as INT6. Bit 4 RXD1OUT Mode 0: USART1 Synchronous Data Output Mode 0: USART1 Synchronous Data Output. Bit 3 RXD0OUT Mode 0: USART0 Synchronous Data Output Mode 0: USART0 Synchronous Data Output. Bit 2-0 T2OUT, T1OUT, T0OUT Serial Data Serial mode 0 provides synchronous, half-duplex serial communication.
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EZ-USB FX2 Technical Reference Manual Bit 5 LASTRD Last Data Read To read data over the I²C compatible bus, a bus master floats the SDA line and issues clock pulses on the SCL line. After every eight bits, the master drives SDA low for one clock to indicate ACK. To signal the last byte of the read transfer, the master floats SDA at ACK time to instruct the slave to stop sending. This is controlled by setting LastRD=1 before reading the last byte of a read transfer.
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15.8.5 I²C-Compatible Bus Data I2DAT I²C-Compatible Bus Data E679 b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Figure 15-60. I²C-Compatible Bus Data Bit 7-0 Data Data Bits Eight bits of data; triggers bus transactions. 15.8.
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EZ-USB FX2 Technical Reference Manual Bit 0 400KHZ High-speed I²C Compatible Bus For I²C-compatible peripherals that support it, the I²C-compatible bus can run at 400 KHz. For compatibility, the bus powers-up at the 100-KHz frequency. If 400KHZ=0, the I²C-compatible bus operates at approximately 100 KHz. If 400KHZ=1, the I²C-compatible bus operates at approximately 400 KHz. This bit is copied to the I²CCTL register bit 0, which is read-write to the firmware.
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15.9 UDMA CRC Registers For complete Flowstate / UDMA information, please contact the Cypress Semiconductor Applications Department. UDMACRCH E67D see Section 15.14 b7 b6 b5 b4 b3 b2 b1 b0 CRC[15:8] RW RW RW RW RW RW RW RW 0 1 0 0 1 0 1 0 UDMACRCL E67E see Section 15.14 b7 b6 b5 b4 b3 b2 b1 b0 CRC[7:0] RW RW RW RW RW RW RW RW 1 0 1 1 1 0 1 0 These two registers are strictly for debug purposes.
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EZ-USB FX2 Technical Reference Manual UDMACRCQUALIFIER E67F b7 b6 b5 b4 b3 b2 b1 b0 QENABLE 0 0 0 QSTATE RW R R R RW RW RW RW 0 0 0 0 0 0 0 0 QSIGNAL[2:0] This register only applies to UDMA IN transactions that are host terminated. Otherwise, this register can be completely ignored. This register covers a very specific and potentially nonexistent (from a typical system implementation standpoint*) UDMA CRC situation.
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15.10 USB Control 15.10.1 USB Control and Status USBCS USB Control and Status E680 b7 b6 b5 b4 b3 b2 b1 b0 HSM 0 0 0 DISCON NOSYNSOF RENUM SIGRSUME R R R R R/W R/W R/W R/W x 0 0 0 0 0 0 0 Figure 15-63. USB Control and Status Bit 7 HSM High Speed Mode If HSM=1, the SIE is operating in High Speed Mode, 480 bits/sec. 0-1 transition of this bit causes a HSGRANT interrupt request.
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EZ-USB FX2 Technical Reference Manual Bit 0 SIGRSUME Signal Remote Device Resume Set SIGRSUME=1 to drive the “K” state onto the USB bus. This should be done only by a device that is capable of remote wakeup, and then only during the SUSPEND state. To signal RESUME, set SIGRSUME=1, waits 10-15 ms, then sets SIGRSUME=0. 15.10.
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Bit 6 WU Wakeup Initiated from WU Pin The FX2 sets this bit to1 when wakeup was initiated by the WU pin. Write a 1 to this bit to clear it. Bit 5 WU2POL Polarity of WU2 Pin Polarity of the WU2 input pin. 0 = active low, 1 = active high. Bit 4 WUPOL Polarity of WU Pin Polarity of the WU input pin. 0 = active low, 1 = active high. Bit 2 DPEN Enable/Disable DPLUS Wakeup Activity on the USB DPLUS signal normally initiates a USB wakeup sequence.
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EZ-USB FX2 Technical Reference Manual Bit 6 S Set Data Toggle to DATA1 After selecting the desired endpoint by writing the endpoint select bits (IO and EP3:0), set S=1 to set the data toggle to DATA1. The endpoint selection bits should not be changed while this bit is written. Bit 5 R Set Data Toggle to DATA0 Set R=1 to set the data toggle to DATA0. The endpoint selection bits should not be changed while this bit is written.
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15.10.6 USB Frame Count Low USBFRAMEL USB Frame Count LOW E685 b7 b6 b5 b4 b3 b2 b1 b0 FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 R R R R R R R R x x x x x x x x Figure 15-68. USB Frame Count Low Bit 7-0 FC7:0 Low Byte for USB Frame Count Every millisecond the host sends a SOF token indicating “Start Of Frame,” along with an 11-bit incrementing frame count. The EZ-USB FX2 copies the frame count into these registers at every SOF.
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EZ-USB FX2 Technical Reference Manual 15.10.8 USB Function Address FNADDR USB Function Address E687 b7 b6 b5 b4 b3 b2 b1 b0 0 FA6 FA5 FA4 FA3 FA2 FA1 FA0 R R R R R R R R 0 0 0 0 0 0 0 0 Figure 15-70. USB Function Address Bit 6-0 FA6:0 USB Function Address During the USB enumeration process, the host sends a device a unique 7-bit address, which the USB core copies into this register.
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The SIE normally determines how many bytes to send over EP0 in response to a device request by taking the smaller of (a) the wLength field in the SETUP packet, and (b) the number of bytes available for transfer (byte count). 15.11.2 Endpoint 0 Control and Status (Byte Count Low) EP0BCL Endpoint 0 Byte Count Low E68B b7 b6 b5 b4 b3 b2 b1 b0 (BC7) BC6 BC5 BC4 BC3 BC2 BC1 BC0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Figure 15-72.
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EZ-USB FX2 Technical Reference Manual 15.11.4 Endpoint 2 and 6 Byte Count High EP2BCH Endpoint 2 Byte Count HIGH E690 Endpoint 6 Byte Count HIGH E698 see Section 15.14 EP6BCH see Section 15.14 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 BC10 BC9 BC8 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 x x x Figure 15-74. Endpoint 2 and 6 Byte Count High Bit 1-0 BC9:8 Endpoint 2, 6 Byte Count High EP2 and EP6 can be either 512 or 1024 bytes. These are the high 2 bits of the byte-count.
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15.11.6 Endpoint 2, 4, 6, 8 Byte Count Low EP2BCL Endpoint 2 Byte Count LOW E691 Endpoint 4 Byte Count LOW E695 Endpoint 6 Byte Count LOW E699 Endpoint 8 Byte Count LOW E69D see Section 15.14 EP4BCL see Section 15.14 EP6BCL see Section 15.14 EP8BCL see Section 15.14 b7 b6 b5 b4 b3 b2 b1 b0 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Figure 15-76.
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EZ-USB FX2 Technical Reference Manual off completing the CONTROL transfer until the device has had time to respond to a request.Clear the HSNAK bit (by writing “1” to it) to instruct the USB core to ACK the status stage of the transfer. Bit 1 BUSY EP0 Buffer Busy BUSY is a read-only bit that is automatically cleared when a SETUP token arrives. The BUSY bit is set by writing a byte count to EP0BCL.
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EP1OUTBUF is available for the firmware to read. USB OUT tokens for the endpoint are NAK’d while BUSY=1 (the firmware is still reading data from the OUT endpoint). A 1-to-0 transition of BUSY (indicating that the firmware can access the buffer) generates an interrupt request for the OUT endpoint. After the firmware reads the data from the OUT endpoint buffer, it loads the endpoint’s byte count register with any value to re-arm the endpoint, which automatically sets BUSY=1.
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EZ-USB FX2 Technical Reference Manual 15.11.9 Endpoint 2 Control and Status EP2CS Endpoint 2 Control and Status E6A3 b7 b6 b5 b4 b3 b2 b1 b0 0 NPAK2 NPAK1 NPAK0 FULL EMPTY 0 STALL R R R R R R R R/W 0 0 1 0 1 0 0 0 Figure 15-79. Endpoint 2 Control and Status Bit 6-4 NPAK2:0 Number of Packets in FIFO The number of packets in the FIFO. 0-4 Packets. Bit 3 FULL Endpoint FIFO Full This bit is set to “1” to indicate that the Endpoint FIFO is full.
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Bit 5-4 NPAK1:0 Number of Packets in FIFO The number of packets in the FIFO. 0-2 Packets. Bit 3 FULL Endpoint FIFO Full This bit is set to “1” to indicate that the Endpoint FIFO is full. Bit 2 EMPTY Endpoint FIFO Empty This bit is set to “1” to indicate that the Endpoint FIFO is empty. Bit 0 STALL ENDPOINT STALL Set this bit to “1” to stall an endpoint, and to “0” to clear a stall. When the stall bit is “1,” the USB core returns a STALL handshake for all requests to the endpoint.
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EZ-USB FX2 Technical Reference Manual 15.11.12 Endpoint 8 Control and Status EP8CS Endpoint 8 Control and Status E6A6 b7 b6 b5 b4 b3 b2 b1 b0 0 0 NPAK1 NPAK0 FULL EMPTY 0 STALL R R R R R R R R/W 0 0 0 0 0 1 0 0 Figure 15-82. Endpoint 8 Control and Status Bit 5-4 NPAK1:0 Number of Packets in FIFO The number of packets in the FIFO. 0-2 Packets. Bit 3 FULL Endpoint FIFO Full This bit is set to “1” to indicate that the Endpoint FIFO is full.
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15.11.13 Endpoint 2 and 4 Slave FIFO Flags EP2FIFOFLGS EP4FIFOFLGS Endpoint 2 Slave FIFO Flags Endpoint 4 Slave FIFO Flags E6A7 E6A8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 PF EF FF R R R R R R R R 0 0 0 0 0 0 1 0 Figure 15-83. Endpoint 2 and 4 Slave FIFO Flags Bit 2 PF Programmable Flag State of the EP2/EP4 Programmable Flag. Bit 1 EF Empty Flag State of the EP2/EP4 Empty Flag. Bit 0 FF Full Flag State of the EP2/EP4 Full Flag.
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EZ-USB FX2 Technical Reference Manual Bit 2 PF Programmable Flag State of the EP6/EP8 Programmable Flag. The default value is different from EP2FIFOFLGS.PF and EP4FIFOFLGS.PF. Bit 1 EF Empty Flag State of the EP6/EP8 Empty Flag. Bit 0 FF Full Flag State of the EP6/EP8 Full Flag. FIFOPINPOLAR settings do not affect the behavior of these bits. 15.11.
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Bit 3-0 BC11:8 Byte Count High Total number of bytes in Endpoint FIFO. Maximum of 2048 bytes. 15.11.17 Endpoint 4 and 8 Slave FIFO Byte Count High EP4FIFOBCH EP8FIFOBCH Endpoint 4 Slave FIFO Total Byte Count HIGH Endpoint 8 Slave FIFO Total Byte Count HIGH E6AD E6B1 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 BC10 BC9 BC8 R R R R R R R R 0 0 0 0 0 0 0 0 Figure 15-87.
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EZ-USB FX2 Technical Reference Manual 15.11.19 Setup Data Pointer High and Low Address SUDPTRH Setup Data Pointer High Address Byte E6B3 b7 b6 b5 b4 b3 b2 b1 b0 A15 A14 A13 A12 A11 A10 A9 A8 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Figure 15-89.
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15.11.20 Setup Data Pointer Auto SUDPTRCTL Setup Data Pointer AUTO Mode E6B5 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 SDPAUTO R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 1 Figure 15-91. Setup Data Pointer AUTO Mode Bit 0 SDPAUTO Setup Data Pointer Auto Mode To send a block of data using the Setup Data Pointer, the block’s starting address is loaded into SUDPTRH:L.
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EZ-USB FX2 Technical Reference Manual 15.11.21 Setup Data - 8 Bytes SETUPDAT 8 Bytes of Setup Data E6B8-E6BF b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R R R R R R R R x x x x x x x x Figure 15-92.
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15.12 General Programmable Interface (GPIF) 15.12.1 GPIF Waveform Selector GPIFWFSELECT b7 Waveform Selector b6 b5 b4 E6C0 b3 SINGLEWR1 SINGLEWR0 SINGLERD1 SINGLERD0 FIFOWR1 b2 b1 b0 FIFOWR0 FIFORD1 FIFORD0 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 0 0 1 0 0 Figure 15-93. GPIF Waveform Selector Bit 7-6 SINGLEWR1:0 Single Write Waveform Index Index to the Waveform Program to run when a “Single Write” is triggered by the firmware.
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EZ-USB FX2 Technical Reference Manual Bit 7 DONE GPIF Idle State 0 = Transaction in progress. 1 = Transaction Done (GPIF is idle, hence GPIF is ready for next Transaction). Fires IRQ4 if enabled. Bit 0 IDLEDRV Set Data Bus when GPIF Idle When the GPIF is idle: 0 = Tri-state the Data Bus. 1 = Drive the Data Bus. 15.12.
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The GPIF Control pins (CTL[5:0]) have several output modes: • CTL[3:0] can act as CMOS outputs (optionally tristatable) or open-drain outputs. • CTL[5:4] can act as CMOS outputs or open-drain outputs. If CTL[3:0] are configured to be tristatable, CTL[5:4] are not available. Table 15-16. CTL[5:0] Output Modes TRICTL (GPIFCTLCFG.
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EZ-USB FX2 Technical Reference Manual Table 15-17 illustrates this relationship. Table 15-17. Control Outputs (CTLx) During the IDLE State TRICTL Control Output 0 1 Output State Output Enable CTL0 GPIFIDLECTL.0 CTL1 GPIFIDLECTL.1 CTL2 GPIFIDLECTL.2 CTL3 GPIFIDLECTL.3 CTL4 GPIFIDLECTL.4 CTL5 GPIFIDLECTL.5 CTL0 GPIFIDLECTL.0 GPIFIDLECTL.4 CTL1 GPIFIDLECTL.1 GPIFIDLECTL.5 CTL2 GPIFIDLECTL.2 GPIFIDLECTL.6 CTL3 GPIFIDLECTL.3 GPIFIDLECTL.
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15.12.5 GPIF Address Low GPIFADRL GPIF Address Low E6C5 see Section 15.14 b7 b6 b5 b4 b3 b2 b1 b0 GPIFA7 GPIFA6 GPIFA5 GPIFA4 GPIFA3 GPIFA2 GPIFA1 GPIFA0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Figure 15-98. GPIF Address Low Bit 7-0 GPIFA7:0 Lower 8 bits of GPIF Address Data written to this register immediately appears as the bus address on the ADR[7:0] pins. 15.12.
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EZ-USB FX2 Technical Reference Manual FLOWLOGIC b7 E6C7 b6 b5 LFUNC[1:0] b4 b3 b2 TERMA[2:0] b1 b0 TERMB[2:0] 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW The bit definitions for this register are analogous to the bit definitions in the RDY LOGIC opcode in a waveform descriptor. Except, instead of controlling the branching for a decision point, it controls the freezing or flowing of data on the bus in a flow state.
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Bits 5-3 Bits 2-0 TERMA[2:0] TERMB[2:0] Flow State Logic-Function Arguments 0 = RDY[0] 1 = RDY[1] 2 = RDY[2] 3 = RDY[3] 4 = RDY[4] 5 = RDY[5] or TC-Expiration (depending on GPIF_READYCFG.5) 6 = FIFO Flag (PF, EF, or FF depending on GPIF_EPxFLAGSEL) 7 = 8051 RDY (GPIF_READYCFG.
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EZ-USB FX2 Technical Reference Manual CTLx Bit: specifies the state to set each CTLx signal to during this entire State. 1 = High level If the CTLx bit in the GPIFCTLCFG register is set to 1, the output driver will be an open-drain. If the CTLx bit in the GPIFCTLCFG register is set to 0, the output driver will be driven to CMOS levels. 0 = Low level defined by FLOWEQxCTL and these bits, instead: • TRICTL (GPIFCTLCFG.7), as described in Section 10.2.3.1, "Control Output Modes". • GPIFCTLCFG[5:0].
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Table 15-18. Control Outputs (CTLx) During the Flow State TRICTL Drive Type (0 = CMOS, 1 = Open-Drain) Control Output Output State CTL0 FLOWEQxCTL.0 GPIFCTLCFG.0 CTL1 FLOWEQxCTL.1 GPIFCTLCFG.0 CTL2 FLOWEQxCTL.2 GPIFCTLCFG.0 CTL3 FLOWEQxCTL.3 GPIFCTLCFG.0 CTL4 FLOWEQxCTL.4 GPIFCTLCFG.0 CTL5 FLOWEQxCTL.5 GPIFCTLCFG.0 CTL0 FLOWEQxCTL.0 0 1 CTL1 FLOWEQxCTL.1 CTL2 FLOWEQxCTL.2 CTL3 FLOWEQxCTL.3 CTL4 Output Enable N/A (CTL Outputs are always enabled when TRICTL = 0) FLOWEQxCTL.
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EZ-USB FX2 Technical Reference Manual 1: GPIF is the slave of the bus transaction. This means that one of the RDY[5:0] pins will be the Master Strobe and the particular one is selected by MSTB[2:0]. Bit 6 RDYASYNC If SLAVE is 0 then this bit is ignored, otherwise: 0: Master Strobe (which is a RDY pin in this case) is asynchronous to IFCLK. 1: Master Strobe (which is a RDY pin in this case) is synchronous to IFCLK. Bit 5 CTLTOGL If SLAVE is 1 then this bit is ignored.
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4. the rate at which data is being written in exceeds 96 MB/s for a word-wide data bus or 48 MB/s for a byte-wide data bus. Bits 7-4 HOPERIOD[3:0] Defines how many IFCLK cycles to assert not ready (HOCTL) to the external master in order to allow the synchronization interface to catch up. Bit 3 HOSTATE Defines what the state of the HOCTL signal should be in to assert not ready.
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EZ-USB FX2 Technical Reference Manual FLOWSTBHPERIOD E6CD b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 RW RW RW RW RW RW RW RW 0 0 0 0 0 0 1 0 If the flow state is such that the GPIF is the master on the bus (FLOWSTB.SLAVE = 0) then Master Strobe will be one of the CTL[5:0] pins (see FLOWSTB). While in the flow state, if the flow logic (see FLOWLOGIC) evaluates in such a way that Master Strobe should toggle (see FLOWSTB.
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this case. It is with respect to when the data would normally come out in response to Master Strobe including any latency to synchronize Master Strobe. In all cases, the data will be held for the desired amount even if the ensuing GPIF state calls for the data bus to be tristated. In other words the FD[15:0] output enable will be held by the same amount as the data itself. Bits 1-0 HOLDTIME[1:0] GPIF Hold Time 00 = 0 IFCLK cycles 01 = ½ IFCLK cycle 10 = 1 IFCLK cycle 11 = Reserved 15.12.
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EZ-USB FX2 Technical Reference Manual Bit 7-0 TC16:23 GPIF Transaction Count Refer to Bit 0 of this register. GPIFTCB1 GPIF Transaction Count Byte1 E6D0 see Section 15.14 b7 b6 b5 b4 b3 b2 b1 b0 TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Figure 15-101. GPIF Transaction Count Byte1 Bit 7-0 TC8:15 GPIF Transaction Count Refer to Bit 0 of this register. GPIFTCB0 GPIF Transaction Count Byte0 E6D1 see Section 15.
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15.12.8 Endpoint 2, 4, 6, 8 GPIF Flag Select EP2GPIFFLGSEL Endpoint 2 GPIF Flag Select E6D2 Endpoint 4 GPIF Flag Select E6DA Endpoint 6 GPIF Flag Select E6E2 Endpoint 8 GPIF Flag Select E6EA see Section 15.14 EP4GPIFFLGSEL see Section 15.14 EP6GPIFFLGSEL see Section 15.14 EP8GPIFFLGSEL see Section 15.14 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 FS1 FS0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Figure 15-103.
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EZ-USB FX2 Technical Reference Manual 15.12.9 Endpoint 2, 4, 6, and 8 GPIF Stop Transaction EP2GPIFPFSTOP EP4GPIFPFSTOP EP6GPIFPFSTOP EP8GPIFPFSTOP Endpoint 2 GPIF Stop Transaction Endpoint 4 GPIF Stop Transaction Endpoint 6 GPIF Stop Transaction Endpoint 8 GPIF Stop Transaction E6D3 E6DB E6E3 E6EB b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 FIFO[2,4,6,8] FLAG R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Figure 15-104.
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15.12.11 GPIF Data High (16-Bit Mode) XGPIFSGLDATH GPIF Data HIGH (16-bit mode) E6F0 b7 b6 b5 b4 b3 b2 b1 b0 D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Figure 15-106. GPIF Data High (16-Bit Mode) Bit 7-0 D15:8 GPIF Data High Contains the data written to or read from the FD15:8 (PORTD) pins using the GPIF waveform. 15.12.
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EZ-USB FX2 Technical Reference Manual 15.12.13 Read GPIF Data LOW, No Transaction Trigger XGPIFSGLDATLNOX Read GPIF Data LOW, No Transaction Trigger E6F2 b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R R R R R R R R x x x x x x x x Figure 15-108. Read GPIF Data LOW, No Transaction Trigger Bit 7-0 D7:0 GPIF Data Low /Don’t Trigger GPIF Transaction Contains the data written to or read from the FD7:0 (PORTB) pins.
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If the RDY signals are synchronized to IFCLK, and obey the setup and hold times with respect to this clock, the user can set SAS=0, which causes the RDY signals to pass through a single flip-flop. Bit 5 TCXRDY5 TC Expiration Replaces RDY5 To use the transaction count expiration signal as a ready input to a waveform, set this bit to 1. Setting this bit will take the place of the pin RDY5 in the decision point of the waveform.
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EZ-USB FX2 Technical Reference Manual 15.13 Endpoint Buffers 15.13.1 EP0 IN-OUT Buffer EP0BUF EP0 IN/OUT Buffer E740-E77F b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W X X X X X X X X Figure 15-112. EP0 IN/OUT Buffer Bit 7-0 D7:0 EP0 Data EP0 Data buffer (IN/OUT). 64 bytes. 15.13.
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15.13.3 Endpoint 1-IN Buffer EP1INBUF EP1-IN Buffer E7C0-E7FF b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W X X X X X X X X Figure 15-114. EP1-IN Buffer Bit 7-0 D7:0 EP1-IN Buffer EP1-IN Data buffer. 64 bytes. 15.13.
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EZ-USB FX2 Technical Reference Manual 15.13.5 512-byte Endpoint 4/Slave FIFO Buffer EP4FIFOBUF 512-byte EP4/Slave FIFO Buffer F400-F5FF b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W X X X X X X X X Figure 15-116. 512-byte EP4/Slave FIFO Buffer Bit 7-0 D7:0 EP4 Data 512-byte EP4 buffer. 15.13.
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15.13.7 512-byte Endpoint 8/Slave FIFO Buffer EP8FIFOBUF 512-byte EP8/Slave FIFO Buffer FC00-FDFF b7 b6 b5 b4 b3 b2 b1 b0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W X X X X X X X X Figure 15-118. 512-byte EP8/Slave FIFO Buffer Bit 7-0 D7:0 EP8 Data 512-byte EP8 buffer. 15.14 Synchronization Delay Under certain conditions, some read and write accesses to FX2 registers must be separated by a synchronization delay.
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EZ-USB FX2 Technical Reference Manual The minimum delay length is a function of the IFCLK and CLKOUT (CPU Clock) frequencies, and is determined by the equation: IFCLK Period 1.5 ×  ----------------------------------------- + 1  CLKOUT Period  Minimum Sync Delay, in CPU cycles = Note: n means “round n upward” The required delay length is smallest when the CPU is running at its slowest speed (12 MHz, 83.2 ns/cycle) and IFCLK is running at its fastest speed (48 MHz, 20.8 ns/cycle).
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Appendix A Default Descriptors for Full Speed Mode Tables A-1 through A-25 show the descriptor data built into the FX2 logic. The tables are presented in the order that the bytes are stored. Table A-1 Default USB Device Descriptor Offset Field Description Value 0 bLength Length of this Descriptor = 18 bytes 12H 1 bDescriptorType Descriptor Type = Device 01H 2 bcdUSB (L) USB Specification Version 2.00 (L) 00H 3 bcdUSB (H) USB Specification Version 2.
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EZ-USB FX2 Technical Reference Manual Table A-2 Device Qualifier Offset Field Description Value 0 bLength Length of this Descriptor = 10 bytes 0AH 1 bDescriptorType Descriptor Type = Device Qualifier 06H 2 bcdUSB (L) USB Specification Version 2.00 (L) 00H 3 bcdUSB (H) USB Specification Version 2.
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Table A-4 USB Default Interface 0, Alternate Setting 0 Offset Field Description Value 0 bLength Length of the Interface Descriptor 09H 1 bDescriptorType Descriptor Type = Interface 04H 2 bInterfaceNumber Zero based index of this interface = 0 00H 3 bAlternateSetting Alternate Setting Value = 0 00H 4 bNumEndpoints Number of endpoints in this interface (not counting EP0) = 0 00H 5 bInterfaceClass Interface Class = Vendor Specific FFH 6 bInterfaceSubClass Interface Sub-class = Ven
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EZ-USB FX2 Technical Reference Manual Table A-7 Endpoint Descriptor (EP1 in) Offset Field Description Value 0 bLength Length of this Endpoint Descriptor 07H 1 bDescriptorType Descriptor Type = Endpoint 05H 2 bEndpointAddress Endpoint Direction (1 is in) and address = IN1 81H 3 bmAttributes XFR Type = BULK 02H 4 wMaxPacketSize (L) Maximum Packet Size = 64 bytes 40H 5 WMaxPacketSize (H) Maximum Packet Size - High 00H 6 bInterval Polling Interval in Milliseconds (1 for iso) 00H
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Table A-10 Endpoint Descriptor (EP6) Offset Field Description Value 0 bLength Length of this Endpoint Descriptor 07H 1 bDescriptorType Descriptor Type = Endpoint 05H 2 bEndpointAddress Endpoint Direction (1 is in) and address = IN6 86H 3 bmAttributes XFR Type = BULK 02H 4 wMaxPacketSize (L) Maximum Packet Size = 64 bytes 40H 5 WMaxPacketSize (H) Maximum Packet Size - High 00H 6 bInterval Polling Interval in Milliseconds (1 for iso) 00H Table A-11 Endpoint Descriptor (EP8) Off
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EZ-USB FX2 Technical Reference Manual Table A-13 Endpoint Descriptor (EP1 out) Offset Field Description Value 0 bLength Length of this Endpoint Descriptor 07H 1 bDescriptorType Descriptor Type = Endpoint 05H 2 bEndpointAddress Endpoint Direction (1 is in) and address = OUT1 01H 3 bmAttributes XFR Type = INT 03H 4 wMaxPacketSize (L) Maximum Packet Size = 64 bytes 40H 5 WMaxPacketSize (H) Maximum Packet Size - High 00H 6 bInterval Polling Interval in Milliseconds (1 for iso) 0A
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Table A-16 Endpoint Descriptor (EP4) Offset Field Description Value 0 bLength Length of this Endpoint Descriptor 07H 1 bDescriptorType Descriptor Type = Endpoint 05H 2 bEndpointAddress Endpoint Direction (1 is in) and address = OUT4 04H 3 bmAttributes XFR Type = BULK 02H 4 wMaxPacketSize (L) Maximum Packet Size = 64 bytes 40H 5 WMaxPacketSize (H) Maximum Packet Size - High 00H 6 bInterval Polling Interval in Milliseconds (1 for iso) 00H Table A-17 Endpoint Descriptor (EP6) Of
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EZ-USB FX2 Technical Reference Manual Table A-19 Interface Descriptor (Alt.
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Table A-22 Endpoint Descriptor (EP2) Offset Field Description Value 0 bLength Length of this Endpoint Descriptor 07H 1 bDescriptorType Descriptor Type = Endpoint 05H 2 bEndpointAddress Endpoint Direction (1 is in) and address = OUT2 02H 3 bmAttributes XFR Type = ISO, No Synchronization, Data endpoint 01H 4 wMaxPacketSize (L) Maximum Packet Size = 64 bytes 40H 5 WMaxPacketSize (H) Maximum Packet Size - High 00H 6 bInterval Polling Interval in Milliseconds (1 for iso) 01H Table
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EZ-USB FX2 Technical Reference Manual Table A-25 Endpoint Descriptor (EP8) Offset A - 10 Field Description Value 0 bLength Length of this Endpoint Descriptor 07H 1 bDescriptorType Descriptor Type = Endpoint 05H 2 bEndpointAddress Endpoint Direction (1 is in) and address = IN8 88H 3 bmAttributes XFR Type = BULK 02H 4 wMaxPacketSize (L) Maximum Packet Size = 64 bytes 40H 5 WMaxPacketSize (H) Maximum Packet Size - High 00H 6 bInterval Polling Interval in Milliseconds (1 for iso)
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Appendix B Default Descriptors for High Speed Mode Tables B-1 through B-25 show the descriptor data built into the FX2 logic. The tables are presented in the order that the bytes are stored. Table B-1 Device Descriptor Offset Field Description Value 0 bLength Length of this Descriptor = 18 bytes 12H 1 bDescriptorType Descriptor Type = Device 01H 2 bcdUSB (L) USB Specification Version 2.00 (L) 00H 3 bcdUSB (H) USB Specification Version 2.
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EZ-USB FX2 Technical Reference Manual Table B-2 Device Qualifier Offset Field Description Value 0 bLength Length of this Descriptor = 10 bytes 0AH 1 bDescriptorType Descriptor Type = Device Qualifier 06H 2 bcdUSB (L) USB Specification Version 2.00 (L) 00H 3 bcdUSB (H) USB Specification Version 2.
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Table B-4 Interface Descriptor (Alt.
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EZ-USB FX2 Technical Reference Manual Table B-7 Endpoint Descriptor (EP1 in) Offset Field Description Value 0 bLength Length of this Endpoint Descriptor 07H 1 bDescriptorType Descriptor Type = Endpoint 05H 2 bEndpointAddress Endpoint Direction (1 is in) and address = IN1 81H 3 bmAttributes XFR Type = BULK 02H 4 wMaxPacketSize (L) Maximum Packet Size = 512 bytes 00H 5 WMaxPacketSize (H) Maximum Packet Size - High 02H 6 bInterval Polling Interval in Milliseconds (1 for iso) 00H
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Table B-10 Endpoint Descriptor (EP6) Offset Field Description Value 0 bLength Length of this Endpoint Descriptor 07H 1 bDescriptorType Descriptor Type = Endpoint 05H 2 bEndpointAddress Endpoint Direction (1 is in) and address = IN6 86H 3 bmAttributes XFR Type = BULK 02H 4 wMaxPacketSize (L) Maximum Packet Size = 512 bytes 00H 5 WMaxPacketSize (H) Maximum Packet Size - High 02H 6 bInterval Polling Interval in Milliseconds (1 for iso) 00H Table B-11 Endpoint Descriptor (EP8) Of
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EZ-USB FX2 Technical Reference Manual Table B-13 Endpoint Descriptor (EP1 out) Offset Field Description Value 0 bLength Length of this Endpoint Descriptor 07H 1 bDescriptorType Descriptor Type = Endpoint 05H 2 bEndpointAddress Endpoint Direction (1 is in) and address = OUT1 01H 3 bmAttributes XFR Type = INT 03H 4 wMaxPacketSize (L) Maximum Packet Size = 64 bytes 40H 5 WMaxPacketSize (H) Maximum Packet Size - High 00H 6 bInterval Polling Interval in Milliseconds (1 for iso) 01
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Table B-16 Endpoint Descriptor (EP4) Offset Field Description Value 0 bLength Length of this Endpoint Descriptor 07H 1 bDescriptorType Descriptor Type = Endpoint 05H 2 bEndpointAddress Endpoint Direction (1 is in) and address = OUT4 04H 3 bmAttributes XFR Type = BULK 02H 4 wMaxPacketSize (L) Maximum Packet Size = 512 bytes 00H 5 WMaxPacketSize (H) Maximum Packet Size - High 02H 6 bInterval Polling Interval in Milliseconds (1 for iso) 00H Table B-17 Endpoint Descriptor (EP6) O
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EZ-USB FX2 Technical Reference Manual Table B-19 Interface Descriptor (Alt.
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Table B-22 Endpoint Descriptor (EP2) Offset Field Description Value 0 bLength Length of this Endpoint Descriptor 07H 1 bDescriptorType Descriptor Type = Endpoint 05H 2 bEndpointAddress Endpoint Direction (1 is in) and address = OUT2 02H 3 bmAttributes XFR Type = ISO, No Synchronization, Data endpoint 01H 4 wMaxPacketSize (L) Maximum Packet Size = 512 bytes 00H 5 WMaxPacketSize (H) Maximum Packet Size - High 02H 6 bInterval Polling Interval in Milliseconds (1 for iso) 01H Tabl
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EZ-USB FX2 Technical Reference Manual Table B-25 Endpoint Descriptor (EP8) Offset Field Description Value 0 bLength Length of this Endpoint Descriptor 07H 1 bDescriptorType Descriptor Type = Endpoint 05H 2 bEndpointAddress Endpoint Direction (1 is in) and address = IN8 88H 3 bmAttributes XFR Type = BULK 02H 4 wMaxPacketSize (L) Maximum Packet Size = 512 bytes 00H 5 WMaxPacketSize (H) Maximum Packet Size - High 02H 6 bInterval Polling Interval in Milliseconds (1 for iso) 00H
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Appendix C FX2 Register Summary The following table is a summary of all the EZ-USB FX2 Registers. In the “b7-b0” columns, bit positions that contain a 0 or a 1 cannot be written to and, when read, always return the value shown (0 or 1). Bit positions that contain “-” are available but unused. The “Default” column shows each register’s power-on-reset value (“x” indicates “undefined”). The “Access” column indicates each register’s read/write accessibility.
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EZ-USB FX2 Technical Reference Manual C - 22 EZ-USB FX2 Technical Reference Manual v2.
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EZ-USB FX2 Registers & Buffers Register Summary Hex Size Name Description GPIF Waveform Memories E400 128 WAVEDATA GPIF Waveform Descriptor 0, 1, 2, 3 data E480 384 reserved GENERAL CONFIGURATION E600 1 CPUCS CPU Control & Status b7 b6 b5 b4 b3 b2 b1 b0 Default Access D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW 0 0 PORTCSTB CLKSPD1 CLKSPD0 CLKINV CLKOE 8051RES E601 1 IFCONFIG Interface Configuration (Ports, GPIF, slave FIFOs) IFCLKSRC 3048MHZ IFCLKOE IFCLKPOL ASYNC GSTATE IFC
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EZ-USB FX2 Registers & Buffers Hex Size Name E608 1 UART230 Description 230 Kbaud internally generated ref. clock b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 b1 230UART1 b0 Default Access Notes 230UART0 00000000 rrrrrrbb If "1", overrides timer inputs to UART. 230 rate valid for any CPU clock rate. FF 00000000 rrbbbbbb 0=active low, 1=active high E609 1 0 PKTEND SLOE SLRD SLWR EF 1 slave FIFO Interface pins polarity Chip Revision 0 E60A FIFOPINPOLAR see Section 15.
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EZ-USB FX2 Registers & Buffers Hex Size Name E620 1 EP2AUTOINLENH see Section 15.14 E621 1 EP2AUTOINLENL see Section 15.14 E622 1 EP4AUTOINLENH see Section 15.14 E623 1 EP4AUTOINLENL see Section 15.14 E624 1 EP6AUTOINLENH see Section 15.14 E625 1 EP6AUTOINLENL see Section 15.14 E626 1 EP8AUTOINLENH see Section 15.14 E627 1 EP8AUTOINLENL see Section 15.14 E630 H.S. E630 F.S. E631 H.S. E631 F.S E632 H.S. E632 F.S E633 H.S. E633 F.S E634 H.S. E634 F.S E635 H.S. E635 F.S E636 H.S. E636 F.S E637 H.S. E637 F.
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EZ-USB FX2 Registers & Buffers Hex Size Name E640 1 EP2ISOINPKTS Description EP2 (if ISO) IN Packets per frame (1-3) b7 0 b6 0 b5 0 b4 0 b3 0 b2 0 b1 INPPF1 b0 INPPF0 E641 1 EP4ISOINPKTS 0 0 0 0 0 0 INPPF1 INPPF0 E642 1 EP6ISOINPKTS 0 0 0 0 0 0 INPPF1 INPPF0 00000001 rrrrrrbb E643 1 EP8ISOINPKTS EP4 (if ISO) IN Packets per frame (1-3) EP6 (if ISO) IN Packets per frame (1-3) EP8 (if ISO) IN Packets per frame (1-3) Default Access Notes 00000001 rrrrrrbb INPPF1:0: 00=illeg
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EZ-USB FX2 Registers & Buffers Hex Size Name E660 1 GPIFIE see Section 15.14 Description GPIF Interrupt Enable E661 1 GPIF Interrupt Request E662 1 GPIFIRQ see Section 15.
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EZ-USB FX2 Registers & Buffers Hex Size Name E682 1 WAKEUPCS E683 1 TOGCTL E684 1 USBFRAMEH E685 1 USBFRAMEL E686 1 MICROFRAME E687 1 FNADDR E688 2 reserved Description Wakeup Control & Status Toggle Control USB Frame count H USB Frame count L Microframe count, 0-7 USB Function address b7 WU2 Q 0 FC7 0 0 b6 WU S 0 FC6 0 FA6 b5 WU2POL R 0 FC5 0 FA5 b4 WUPOL IO 0 FC4 0 FA4 b3 0 EP3 0 FC3 0 FA3 b2 DPEN EP2 FC10 FC2 MF2 FA2 b1 WU2EN EP1 FC9 FC1 MF1 FA1 b0 WUEN EP0 FC8 FC0 MF0 FA0 Default Access xx0001
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EZ-USB FX2 Registers & Buffers Hex Size Name E6A3 1 EP2CS E6A4 1 EP4CS E6A5 1 EP6CS E6A6 1 EP8CS Description Endpoint 2 Control and Status Endpoint 4 Control and Status Endpoint 6 Control and Status Endpoint 8 Control and Status b7 0 0 0 0 b6 NPAK2 0 NPAK2 0 b5 NPAK1 NPAK1 NPAK1 NPAK1 b4 NPAK0 NPAK0 NPAK0 NPAK0 b3 FULL FULL FULL FULL b2 EMPTY EMPTY EMPTY EMPTY b1 0 0 0 0 b0 STALL STALL STALL STALL E6A7 E6A8 E6A9 E6AA E6AB 1 1 1 1 1 EP2FIFOFLGS EP4FIFOFLGS EP6FIFOFLGS EP8FIFOFLGS EP2FIFOBCH 0 0
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EZ-USB FX2 Registers & Buffers Hex Size Name Description SETUPDAT[4:5] = wIndex b7 b6 b5 b4 b3 b2 b1 b0 Default Access Notes word-sized field that varies according to request; typ. used to pass an index or offset number of bytes to transfer if there is a data stage FIFOWR0 0 FIFORD1 0 FIFORD0 IDLEDRV 11100100 10000000 RW RW Select waveform DONE=1: GPIF done (IRQ4). IDLEDRV=1: drive bus, 0:TS DONE duplicated in SFR space, GPIFTRIG bit 7 0=CMOS, 1=open drn.
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EZ-USB FX2 Registers & Buffers Hex Size Name E6DA 1 EP4GPIFFLGSEL see Section 15.14 Description Endpoint 4 GPIF Flag select E6DB 1 EP4GPIFPFSTOP E6DC 1 EP4GPIFTRIG see Section 15.14 reserved reserved reserved EP6GPIFFLGSEL see Section 15.14 3 E6E2 1 E6E3 1 EP6GPIFPFSTOP E6E4 1 EP6GPIFTRIG see Section 15.14 3 reserved reserved reserved EP8GPIFFLGSEL see Section 15.
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EZ-USB FX2 Registers & Buffers Hex Size Name 2048 reserved F000 1024 EP2FIFOBUF F400 512 EP4FIFOBUF F600 512 reserved F800 1024 EP6FIFOBUF Description b7 b6 b5 b4 b3 b2 b1 b0 Default 512/1024-byte EP 2 / slave FIFO buffer (IN or OUT) 512 byte EP 4 / slave FIFO buffer (IN or OUT) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx 512/1024-byte EP 6 / slave FIFO buffer (IN or OUT) 512 byte EP 8 / slave FIFO buffer (IN or OUT) D7 D6 D5 D4 D3 D2 D1 D0 xxx
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EZ-USB FX2 Registers & Buffers Hex 92 Size Name 1 MPAGE(1) Description Upper Addr Byte of MOVX using @R0 / @R1 b7 A15 b6 A14 b5 A13 b4 A12 b3 A11 b2 A10 b1 A9 b0 A8 Default Access Notes 00000000 RW used with the indirect addressing instuction(s), ie. MOVX @R0,A _where MPAGE = upper addr byte and R0 contains lower addr byte _an app.
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EZ-USB FX2 Registers & Buffers Hex B8 B9 BA BB Size Name 1 IP 1 1 reserved EP01STAT(1) 1 GPIFTRIG(1) Description Interrupt Priority (bit addressable) Endpoint 0&1 Status b7 1 b6 PS1 b5 PT2 b4 PS0 b3 PT1 b2 PX1 b1 PT0 b0 PX0 0 0 0 0 0 EP1INBSY EP1OUTBSY EP0BSY DONE 0 0 0 0 RW EP1 EP0 D15 D14 D13 D12 D11 D10 D9 D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 SM0_1 SM1_1 SM2_1 REN_1 TB8_1 Default Access 10000000 RW 00000000 R Check EP0 & EP1 status using MOV instr.