Specifications

CY7C6431x
CY7C6434x
CY7C6435x
Document Number: 001-12394 Rev. *R Page 38 of 40
*F 2583853 TYJ /
PYRS /
HMT
10/10/08 Converted from Preliminary to Final
Added operating voltage ranges with USB
ADC resolution changed from 10-bit to 8-bit
Rephrased battery monitoring clause in page 1 to include “with external
components”
Included ADC specifications table
Included Voh7, Voh8, Voh9, Voh10 specs
Flash data retention – condition added to Note [11]
Input leakage spec changed to 25 nA max
Under AC Char, Frequency accuracy of ILO corrected
GPIO rise time for ports 0,1 and ports 2,3 made common
AC Programming specifications updated
Included AC Programming cycle timing diagram
AC SPI specification updated
Spec change for 32-QFN package
Input Leakage Current maximum value changed to 1 A
Updated V
OHV
parameter in Table 13
Updated thermal impedances for the packages
Update Development Tools, add Designing with PSoC Designer. Edit, fix links
and table format. Update TMs.
*G 2653717 DVJA /
PYRS
02/04/09 Updated Features, Functional Overview, Development Tools, and Designing
with PSoC Designer sections with edits.
Removed ‘GUI - graphical user interface’ from Document Conventions
acronym table.
Removed ‘O - Only a read/write register or bits’ in Table 4
Edited Table 8: removed 10-bit resolution information and corrected units
column.
Added package handling section
Added 8K part ‘CY7C64343-32LQXC’ to Ordering Information.
*H 2714694 DVJA /
AESA
06/04/2009 Updated Block Diagram.
Added Full Speed USB, 10-bit ADC, SPI, and I2C Slave sections.
ADC Resolution changed from 8-bit to 10-bit
Updated Table 9 DC Chip Level Specs
Updated Table10 DC Char - USB Interface
Updated Table 12 DC POR and LDV Specs
Changed operating temperature from Commercial to Industrial
Changed Temperature Range to Industrial: –40 to 85°C
Figure 9: Changed minimum CPU Frequency from 750 kHz to 5.7 MHz
Table 14: Removed “Maximum” from the F
CPU
description
Ordering Information: Replaced ‘C’ with ‘I’ in all part numbers to denote Indus-
trial Temp Range
*I 2764460 DVJA /
AESA
09/16/2009 Changed Table 12: ADC Specs
Added F
32K2
(Untrimmed) spec to Table 16: AC Chip level Specs
Changed T
RAMP
spec to SR
POWER_UP
in Table 16: AC Chip Level Specs
Added Table 27: Typical Package Capacitance on Crystal Pins
*J 2811903 DVJA 11/20/2009 Added USB-IF TID number in Features on page 1. Added Note 5 on page 18.
Changed V
IHP
in Table 15 on page 22.
Document History Page (continued)
Document Title: CY7C6431x, CY7C6434x, CY7C6435x, enCoRe™ V Full Speed USB Controller
Document Number: 001-12394
Rev. ECN No.
Orig. of
Change
Submission
Date
Description of Change