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Specifications

ManualsBrandsCypress Semiconductor ManualsComputer equipmentenCoRe CY7C6435x
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CY7C6431x
CY7C6434x
CY7C6435x
Document Number: 001-12394 Rev. *R Page 35 of 40
Errata
This section describes the errata for the enCoRe V – CY7C643xx. Details include errata trigger conditions, scope of impact, available
workaround, and silicon revision applicability.
Contact your local Cypress Sales Representative if you have questions.
CY7C643xx Errata Summary
The following Errata item applies to the CY7C643xx data sheets.
1. Latch up susceptibility when maximum I/O sink current exceeded
■ PROBLEM DEFINITION
P1[3], P1[6], and P1[7] pins are susceptible to latch up when the I/O sink current exceeds 25 mA per pin on these pins.
■ PARAMETERS AFFECTED
LU – Latch up current. Per JESD78A, the maximum allowable latch up current per pin is 100 mA. Cypress internal specification
is 200 mA latch up current limit.
■ TRIGGER CONDITIONS
Latch up occurs when both the following conditions are met:
A. The offending I/O is externally connected to a voltage higher than the I/O high state, causing a current to flow into the pin
that exceeds 25 mA.
B. A Port1 I/O (P1[1], P1[4], and P1[5] respectively) adjacent to the offending I/O is connected to a voltage lower than the I/O
low state. This causes a signal that drops below Vss (signal undershoot) and a current greater than 200 mA to flow out of
the pin.
■ SCOPE OF IMPACT
The trigger conditions outlined in this item exceed the maximum ratings specified in the CY7C643xx data sheets.
■ WORKAROUND
Add a series resistor > 300 to P1[3], P1[6], and P1[7] pins to restrict current to within latch up limits.
■ FIX STATUS
This issue will be corrected in the next new silicon revision.
2. Does not meet USB 2.0 specification for D+ and D- rise/fall matching when supply voltage is under 3.3 V
■ PROBLEM DEFINITION
Rising to falling rate matching of the USB D+ and D- lines has a corner case at lower supply voltages, such as those under 3.3 V.
■ PARAMETERS AFFECTED
Rising to falling rate matching of the USB data lines.
■ TRIGGER CONDITION(S)
Operating the VCC supply voltage at the low end of the chip’s specification (under 3.3 V) may cause a mismatch in the rising
to falling rate.
■ SCOPE OF IMPACT
This condition does not affect USB communications but could cause corner case issues with USB lines’ rise/fall matching
specification. Signal integrity tests were run using the Cypress development kit and excellent eye was observed with supply
voltage of 3.15 V.