Specifications

ManualsBrandsCypress Semiconductor ManualsComputer equipmentenCoRe CY7C6435x

CY7C6431x

CY7C6434x

CY7C6435x

enCoRe™ V Full Speed USB Controller

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-12394 Rev. *R Revised November 20, 2013

enCoRe™ V Full Speed USB Controller

Features

■ Powerful Harvard-architecture processor

❐ M8C processor speeds running up to 24 MHz

❐ Low power at high processing speeds

❐ Interrupt controller

❐ 3.0 V to 5.5 V operating voltage without USB

❐ Operating voltage with USB enabled:

• 3.15 V to 3.45 V when supply voltage is around 3.3 V

• 4.35 V to 5.25 V when supply voltage is around 5.0 V

❐ Commercial temperature range: 0°C to +70°C

❐ Industrial temperature range: –40 °C to +85 °C

■ Flexible on-chip memory

❐ Up to 32 KB flash program storage:

• 50,000 erase and write cycles

• Flexible protection modes

❐ Up to 2048 bytes SRAM data storage

❐ In-system serial programming (ISSP)

■ Complete development tools

❐ Free development tool PSoC Designer™

❐ Full-featured, in-circuit emulator and programmer

❐ Full-speed emulation

❐ Complex breakpoint structure

❐ 128-KB trace memory

■ Precision, programmable clocking

❐ Crystal-less oscillator with support for an external crystal or

resonator

❐ Internal ±5.0% 6, 12, or 24 MHz main oscillator (IMO):

• 0.25% accuracy with oscillator lock to USB data, no

external components required

• Internal low-speed oscillator (ILO) at 32 kHz for watchdog

and sleep. The frequency range is 19 to 50 kHz with a

32-kHz typical value

■ Programmable pin configurations

❐ Up to 36 general purpose I/O (GPIO) depending on package.

❐ 25 mA sink current on all GPIO

• 60mA total sink current on Even port pins and 60 mA total

sink current on Odd port pins

• 120 mA total sink current on all GPIOs

❐ Pull-up, High Z, open drain, CMOS drive modes on all GPIO

❐ CMOS drive mode A -5 mA source current on ports 0 and 1

and 1 mA on ports 2, 3, and 4

• 20 mA total source current on all GPIOs

❐ Low dropout voltage regulator for Port 1 pins:

• Programmable to output 3.0, 2.5, or 1.8 V

❐ Selectable, regulated digital I/O on Port 1

❐ Configurable input threshold for Port 1

❐ Hot-swappable Capability on Port 1

■ Full-Speed USB (12 Mbps)

❐ Eight unidirectional endpoints

❐ One bidirectional control endpoint

❐ USB 2.0-compliant: TID# 40000893

❐ Dedicated 512 bytes buffer

❐ No external crystal required

■ Additional system resources

❐ Configurable communication speeds

❐ I

C slave:

• Selectable to 50 kHz, 100 kHz, or 400 kHz

• Implementation requires no clock stretching

• Implementation during sleep modes with less than 100 A

• Hardware address detection

❐ SPI master and SPI slave:

• Configurable between 46.9 kHz and 12 MHz

❐ Three 16-bit timers

❐ 10-bit ADC used to monitor battery voltage or other signals

with external components

❐ Watchdog and sleep timers

❐ Integrated supervisory circuit

System Bus

6/12/24 MHz Internal Main Oscillator

CPU Core

(M8C)

SROM

8K/16K/32K Flash

SYSTEM RESOURCES

I2C Slave/SPI

Master-Slave

POR and LVD

System Resets

Port 1 Port 0

Sleep and

Watchdog

Full

Speed

USB

Port 3 Port 2

Prog. LDO

SRAM

2048 Bytes

Interrupt

Controller

enCoRe V

CORE

3 16-Bit

Timers

Port 4

ADC

enCoRe V Block Diagram

Errata: For information on silicon errata, see “Errata” on page 35. Details include trigger conditions, devices affected, and proposed workaround.

Summary of content (40 pages)

PAGE 1
CY7C6431x CY7C6434x CY7C6435x enCoRe™ V Full Speed USB Controller enCoRe™ V Full Speed USB Controller Features ■ Powerful Harvard-architecture processor ❐ M8C processor speeds running up to 24 MHz ❐ Low power at high processing speeds ❐ Interrupt controller ❐ 3.0 V to 5.5 V operating voltage without USB ❐ Operating voltage with USB enabled: • 3.15 V to 3.45 V when supply voltage is around 3.3 V • 4.35 V to 5.25 V when supply voltage is around 5.
PAGE 2
CY7C6431x CY7C6434x CY7C6435x Contents Functional Overview ........................................................ 3 The enCoRe V Core .................................................... 3 Full-Speed USB ........................................................... 3 10-bit ADC ................................................................... 4 SPI ............................................................................... 4 I2C Slave ...................................................................
PAGE 3
CY7C6431x CY7C6434x CY7C6435x Functional Overview Figure 1. USB Transceiver Regulator The enCoRe V family of devices are designed to replace multiple traditional full-speed USB microcontroller system components with one, low cost single-chip programmable component. Communication peripherals (I2C/SPI), a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts. 1.
PAGE 4
CY7C6431x CY7C6434x CY7C6435x Firmware is required to handle various parts of the USB interface. The SIE issues interrupts after key USB events to direct firmware to appropriate tasks: ■ Fill and empty the USB data buffers in USB SRAM. ■ Enable PMA channels appropriately. ■ Coordinate enumeration by decoding USB device requests. ■ Suspend and resume coordination. ■ Verify and select data toggle values. input mux or the temperature sensor with an input voltage range of 0 V to VREFADC.
PAGE 5
CY7C6431x CY7C6434x CY7C6435x SPI configuration register (SPI_CFG) sets master/slave functionality, clock speed, and interrupt select. SPI control register (SPI_CR) provides four control bits and four status bits for device interfacing and synchronization. The SPIM hardware has no support for driving the Slave Select (SS_) signal. The behavior and use of this signal is dependent on the application and enCoRe V device and, if required, must be implemented in firmware.
PAGE 6
CY7C6431x CY7C6434x CY7C6435x Additional System Resources Application Notes System resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include low voltage detection and power on reset. The following statements describe the merits of each system resource. Application notes are an excellent introduction to the wide variety of possible PSoC designs and are available at http://www.cypress.com.
PAGE 7
CY7C6431x CY7C6434x CY7C6435x Development Tools PSoC Designer™ is the revolutionary Integrated Design Environment (IDE) that you can use to customize PSoC to meet your specific application requirements. PSoC Designer software accelerates system design and time to market. Develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment.
PAGE 8
CY7C6431x CY7C6434x CY7C6435x Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed-function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and lowering inventory costs. These configurable resources, called PSoC blocks, have the ability to implement a wide variety of user-selectable functions.
PAGE 9
CY7C6431x CY7C6434x CY7C6435x Pin Configuration The enCoRe V USB device is available in a variety of packages which are listed and illustrated in the subsequent tables. 16-pin Part pinout P2[5] P0[1] P0[3] P0[7] 15 14 13 6 7 8 D+ D– VDD QFN (Top View) 12 11 10 9 5 P1[5] P1[1] 1 2 3 4 VSS P2[3] P1[7] 16 Figure 6. CY7C64315/CY7C64316 16-pin enCoRe V USB Device P0[4] XRES P1[4] P1[0] Table 1. Pin Definitions – 16-pin Part Pinout (QFN) Pin No.
PAGE 10
CY7C6431x CY7C6434x CY7C6435x 32-pin Part Pinout P0[3] P0[5] P0[7] VDD P0[6] P0[4] P0[2] 30 29 28 27 26 25 VSS 32 31 Figure 7. CY7C64343/CY7C64345 32-pin enCoRe V USB Device P2[0] 19 P3[2] P1[3] P1[1] 7 8 18 P3[0] 17 XRES P1[0] D+ 16 20 15 ( Top View) 6 P1[6] 5 P1[5] P1[4] P2[4] P2[2] P1[2] QFN 13 14 P2[1] P1[7] 22 21 12 P2[6] 3 4 11 P0[0] 23 D– VDD 24 2 9 10 1 P2[5] P2[3] VSS P0[1] Table 2. Pin Definitions – 32-pin Part Pinout (QFN) Pin No.
PAGE 11
CY7C6431x CY7C6434x CY7C6435x 48-pin Part Pinout P0[0] 38 37 VDD P0[6] P0[4] P0[2] NC NC 43 42 41 40 39 P0[5] P0[7] 45 44 QFN 19 20 21 22 23 24 VSS D+ DVDD P1[0] P1[2] 36 35 34 33 32 31 30 29 28 27 26 25 P2[6] P2[4] P2[2] P2[0] P4[2] P4[0] P3[6] P3[4] P3[2] P3[0] XRES P1[6] P1[4] 17 18 P1[1] P1[3] NC NC 15 16 (Top View) 13 14 3 4 5 6 7 8 9 10 11 12 46 47 1 2 P1[5] NC P2[7] P2[5] P2[3] P2[1] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P1[7] 48 P0[1] VSS P0[3] Figure 8.
PAGE 12
CY7C6431x CY7C6434x CY7C6435x Table 3. 48-pin Part Pinout (QFN) (continued) Pin No.
PAGE 13
CY7C6431x CY7C6434x CY7C6435x Register Reference The section discusses the registers of the enCoRe V device. It lists all the registers in mapping tables, in address order. Register Conventions Register Mapping Tables The register conventions specific to this section are listed in the following table. The enCoRe V device has a total register address space of 512 bytes. The register space is also referred to as I/O space and is broken into two parts: Bank 0 (user space) and Bank 1 (configuration space).
PAGE 14
CY7C6431x CY7C6434x CY7C6435x Table 5.
PAGE 15
CY7C6431x CY7C6434x CY7C6435x Table 6.
PAGE 16
CY7C6431x CY7C6434x CY7C6435x Electrical Specifications This section presents the DC and AC electrical specifications of the enCoRe V USB devices. For the most up-to-date electrical specifications, verify that you have the most recent data sheet available by visiting the company web site at http://www.cypress.com Figure 9. Voltage versus CPU Frequency Figure 10. IMO Frequency Trim Options 5.5V 5.
PAGE 17
CY7C6431x CY7C6434x CY7C6435x Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 7. Absolute Maximum Ratings Symbol Description [10] Conditions Min Typ Max Units Higher storage temperatures reduces data retention time. Recommended Storage Temperature is +25 °C ± 25 °C. Extended duration storage temperatures above 85C degrades reliability. –55 +25 +125 °C –0.5 – +6.
PAGE 18
CY7C6431x CY7C6434x CY7C6435x DC Electrical Characteristics DC Chip Level Specifications Table 9 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 9. DC Chip Level Specifications Symbol Description Conditions Min Typ Max Units 3.0 – 5.5 V Conditions are VDD = 3.0 V, TA = 25 C, CPU = 24 MHz, No USB/I2C/SPI. – 2.9 4.0 mA Supply current, CPU = 12 MHz Conditions are VDD = 3.0 V, TA = 25 C, CPU = 12 MHz, No USB/I2C/SPI. – 1.7 2.
PAGE 19
CY7C6431x CY7C6434x CY7C6435x Table 10. DC Characteristics – USB Interface Symbol Min Typ Max Units USB D+ pull-up resistance With idle bus 0.900 – 1.575 k Rusba USB D+ pull-up resistance While receiving traffic 1.425 – 3.090 k Vohusb Static output high 2.8 – 3.6 V Volusb Static output low – – 0.3 V Vdi Differential input sensitivity 0.2 – – V Vcm Differential input common mode range 0.8 – 2.5 V Vse Single-ended receiver threshold 0.8 – 2.
PAGE 20
CY7C6431x CY7C6434x CY7C6435x DC General Purpose I/O Specifications Table 12 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and package specific temperature range. Typical parameters apply to 5 V and 3.3 V at 25 °C. These are for design guidance only. Table 12. 3.0 V and 5.
PAGE 21
CY7C6431x CY7C6434x CY7C6435x DC POR and LVD Specifications Table 13 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 13. DC POR and LVD Specifications Symbol VPPOR VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Description Conditions VDD value for PPOR trip[12] PORLEV[1:0] = 10b VDD value for LVD trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Min Typ Max Units – 2.
PAGE 22
CY7C6431x CY7C6434x CY7C6435x AC Electrical Characteristics AC Chip Level Specifications The following tables list guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 15.
PAGE 23
CY7C6431x CY7C6434x CY7C6435x AC General Purpose I/O Specifications Table 18 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 18. AC GPIO Specifications Symbol FGPIO Description GPIO operating frequency TRise23 Rise time, strong mode Ports 2, 3 Rise time, strong mode Ports 0, 1 Fall time, strong mode All Ports TRise01 TFall Conditions Normal strong mode, Ports 0, 1 VDD = 3.0 to 3.6 V, 10% - 90% VDD = 3.0 to 3.6 V, 10% - 90% VDD = 3.0 to 3.
PAGE 24
CY7C6431x CY7C6434x CY7C6435x AC Programming Specifications Table 20 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 20.
PAGE 25
CY7C6431x CY7C6434x CY7C6435x AC I2C Specifications Table 21 lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 21. AC Characteristics of the I2C SDA and SCL Pins Symbol Standard Mode Description Max Min Max Units 0 100 0 400 kHz THDSTAI2C Hold time (repeated) START condition. After this period, the first clock pulse is generated 4.0 – 0.6 – s TLOWI2C LOW period of the SCL clock 4.7 – 1.
PAGE 26
CY7C6431x CY7C6434x CY7C6435x Table 22. SPI Master AC Specifications Symbol FSCLK Description Conditions SCLK clock frequency Min Typ Max Units – – 6 MHz DC SCLK duty cycle – 50 – % TSETUP MISO to SCLK setup time 60 – – ns THOLD SCLK to MISO hold time 40 – – ns TOUT_VAL SCLK to MOSI valid time – – 40 ns TOUT_H SCLK to MOSI hold time 40 – – ns Figure 14.
PAGE 27
CY7C6431x CY7C6434x CY7C6435x Table 23. SPI Slave AC Specifications Min Typ Max Units FSCLK Symbol SCLK clock frequency Description Conditions 0.0469 – 12 MHz TLOW SCLK low time 41.67 – – ns THIGH SCLK high time 41.
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CY7C6431x CY7C6434x CY7C6435x Figure 17. SPI Slave Mode 1 and 3 SPI Slave, modes 1 and 3 TSS_CLK TCLK_SS /SS 1/FSCLK THIGH TLOW SCLK (mode 1) SCLK (mode 3) TOUT_H TSCLK_MISO TSS_MISO MISO (output) MSb TSETUP MOSI (input) Document Number: 001-12394 Rev.
PAGE 29
CY7C6431x CY7C6434x CY7C6435x Package Diagram This section illustrates the packaging specifications for the enCoRe V USB device, along with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the enCoRe V emulation tools and their dimensions, refer to the development kit. Packaging Dimensions Figure 18. 16-pin Chip On Lead (3 × 3 × 0.
PAGE 30
CY7C6431x CY7C6434x CY7C6435x Figure 19. 32-pin QFN (5 × 5 × 0.55 mm) LQ32 3.5 × 3.5 E-Pad (Sawn) Package Outline, 001-42168 001-42168 *E Figure 20. 48-pin QFN (7 × 7 × 1.00 mm) LT48A 5.1 × 5.1 E-Pad (Sawn) Package Outline, 001-13191 001-13191 *G Document Number: 001-12394 Rev.
PAGE 31
CY7C6431x CY7C6434x CY7C6435x Package Handling Some IC packages require baking before they are soldered onto a PCB to remove moisture that may have been absorbed after leaving the factory. A label on the package has details about the actual bake temperature and the minimum bake time to remove this moisture. The maximum bake time is the aggregate time that the parts exposed to the bake temperature. Exceeding this exposure may degrade device reliability. Table 24.
PAGE 32
CY7C6431x CY7C6434x CY7C6435x Ordering Information Table 28. Ordering Code - Commercial Parts Ordering Code Package Information Flash SRAM No.
PAGE 33
CY7C6431x CY7C6434x CY7C6435x Ordering Code Definitions CY 7C64 XXX- XX XXX C/I (T) Tape and reel Temperature range: Commercial/Industrial Package type: LK/LQ/LT: QFN Pb-free Pin count: 16 = 16 pins, 32 = 32 pins, 48 = 48 pins Base part number Marketing Code: 7C64 = enCoRe Full-Speed USB Controller Company ID: CY = Cypress Document Number: 001-12394 Rev.
PAGE 34
CY7C6431x CY7C6434x CY7C6435x Acronyms Acronym Document Conventions Description API Application Programming Interface CPU Central Processing Unit GPIO General Purpose I/O ICE In-Circuit Emulator ILO Internal Low speed Oscillator IMO Internal Main Oscillator I/O Input/Output LSb Least Significant Bit LVD Low Voltage Detect MSb Most Significant Bit POR Power On Reset PPOR Precision Power On Reset PSoC Programmable System-on-Chip SLIMO Slow IMO SRAM Static Random Access Memory U
PAGE 35
CY7C6431x CY7C6434x CY7C6435x Errata This section describes the errata for the enCoRe V – CY7C643xx. Details include errata trigger conditions, scope of impact, available workaround, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions. CY7C643xx Errata Summary The following Errata item applies to the CY7C643xx data sheets. 1.
PAGE 36
CY7C6431x CY7C6434x CY7C6435x Figure 21. Eye Diagram ■ ■ WORKAROUND Avoid the trigger condition by using lower tolerance voltage regulators. FIX STATUS This issue will not be corrected in the next new silicon revision. Document Number: 001-12394 Rev.
PAGE 37
CY7C6431x CY7C6434x CY7C6435x Document History Page Document Title: CY7C6431x, CY7C6434x, CY7C6435x, enCoRe™ V Full Speed USB Controller Document Number: 001-12394 Rev. ECN No. Orig. of Change Submission Date ** 626256 TYJ See ECN New data sheet. *A 735718 TYJ / ARI See ECN Filled in TBDs, added new block diagram, and corrected some values. Part numbers updated as per new specifications. *B 1120404 ARI See ECN Corrected the block diagram and Figure 3, which is the 16-pin enCoRe V device.
PAGE 38
CY7C6431x CY7C6434x CY7C6435x Document History Page (continued) Document Title: CY7C6431x, CY7C6434x, CY7C6435x, enCoRe™ V Full Speed USB Controller Document Number: 001-12394 Rev. ECN No. Orig.
PAGE 39
CY7C6431x CY7C6434x CY7C6435x Document History Page (continued) Document Title: CY7C6431x, CY7C6434x, CY7C6435x, enCoRe™ V Full Speed USB Controller Document Number: 001-12394 Rev. ECN No. Orig. of Change Submission Date Description of Change *K 2874274 KKU / PYRS 02/05/10 On page 4, changed the input voltage range from ‘0 V to 1.3 V’ to ‘0 V to VREFADC’. Added note for Operating Voltage in Table 9. Updated Register Map.
PAGE 40
CY7C6431x CY7C6434x CY7C6435x Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.