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ManualsBrandsCypress Semiconductor ManualsComputer equipmentenCoRe CY7C601xx

enCoRe™ II Low Voltage

Microcontrolle

CY7C601xx

CY7C602xx

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document 38-16016 Rev. *C Revised October 23, 2006

Features

•enCoRe™ II Low Voltage (enCoRe II LV)—“enhanced

Component Reduction”

— Internal crystalless oscillator with support for optional

external clock or external crystal or resonator.

— Configurable IO for real-world interface without external

components

• Enhanced 8-bit microcontroller

— Harvard architecture

— M8C CPU speed can be up to 12 MHz or sourced by an

external crystal, resonator, or clock signal

• Internal memory

— 256 bytes of RAM

— 8 Kbytes of Flash including EEROM emulation

• Low power consumption

— Typically 2.25 mA at 3 MHz

—5 µA sleep

• In-system reprogrammability

— Allows easy firmware update

• General-purpose I/O ports

— Up to 36 General Purpose I/O (GPIO) pins

— High current drive on GPIO pins. Configurable 8- or 50-

mA/pin current sink on designated pins

— Each GPIO port supports high-impedance inputs, config-

urable pull-up, open drain output, CMOS/TTL inputs, and

CMOS output

— Maskable interrupts on all I/O pins

• SPI serial communication

— Master or slave operation

— Configurable up to 2-Mbit/second transfers.

— Supports half duplex single data line mode for optical

sensors

• 2-channel 8-bit or 1-channel 16-bit capture timer registers.

Capture timer registers store both rising and falling edge

times

— Two registers each for two input pins

— Separate registers for rising and falling edge capture

— Simplifies interface to RF inputs for wireless applications

• Internal low-power wake-up timer during suspend mode

— Periodic wake-up with no external components

• Programmable Interval Timer interrupts

• Reduced RF emissions at 27 MHz and 96 MHz

• Watchdog timer (WDT)

• Low voltage detection with user-selectable threshold

voltages

• Improved output drivers to reduce EMI

• Operating voltage from 2.7V to 3.6VDC

• Operating temperature from 0–70°C

• Available in 24/40-pin PDIP, 24-pin SOIC, 24-pin

QSOP/SSOP, 28-pin SSOP and 48-pin SSOP.

• Advanced development tools based on Cypress PSoC

tools

• Industry-standard programmer support

Applications

The CY7C601xx/CY7C602xx is targeted for the following

applications:

• PC Wireless HID devices

— Mice (optomechanical, optical, trackball)

— Keyboards

— Presenter tools

•Gaming

— Joysticks

— Gamepad

• General purpose wireless applications

— Remote controls

— Barcode scanners

— POS terminal

— Consumer electronics

—Toys

Introduction

The enCoRe II LV family brings the features and benefits of the

enCoRe II to non-USB applications. The enCoRe II family has

an integrated oscillator that eliminates the external crystal or

resonator, reducing overall cost. Other external components,

such as wake-up circuitry, are also integrated into this chip.

The enCoRe II LV is a low-voltage, low-cost 8-bit Flash-

programmable microcontroller

The enCoRe II LV features up to 36 general-purpose I/O

(GPIO) pins. The I/O pins are grouped into five ports (Port 0 to

4). The pins on Port 0 and Port 1 may each be configured

individually while the pins on Ports 2, 3, and 4 may only be

configured as a group. Each GPIO port supports high-

impedance inputs, configurable pull up, open drain output,

CMOS/TTL inputs, and CMOS output with up to five pins that

support programmable drive strength of up to 50 mA sink

current. Additionally, each I/O pin can be used to generate a

GPIO interrupt to the microcontroller. Each GPIO port has its

own GPIO interrupt vector with the exception of GPIO Port 0.

GPIO Port 0 has in addition to the port interrupt vector, three

dedicated pins that have independent interrupt vectors

(P0.2–P0.4).

Summary of content (62 pages)

PAGE 1
CY7C601xx CY7C602xx enCoRe™ II Low Voltage Microcontroller Features • enCoRe™ II Low Voltage (enCoRe II LV)—“enhanced Component Reduction” — Internal crystalless oscillator with support for optional external clock or external crystal or resonator. — Configurable IO for real-world interface without external components • Enhanced 8-bit microcontroller • • • • Improved output drivers to reduce EMI Operating voltage from 2.7V to 3.
PAGE 2
CY7C601xx CY7C602xx The enCoRe II LV features an internal oscillator. Optionally, an external 1 MHz to 24 MHz crystal can be used to provide a higher precision reference. The enCoRe II LV also supports external clock The enCoRe II LV has 8 Kbytes of Flash for user’s code and 256 bytes of RAM for stack space and user variables. In addition, enCoRe II LV includes a Watchdog timer, a vectored interrupt controller, a 16-bit Free-Running Timer with Capture registers and a 12-bit Programmable Interval Timer.
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CY7C601xx CY7C602xx Packages/Pinouts Figure 2. Package Configurations Top View CY7C60223 24-pin PDIP P3.0 P3.1 SCLK/P1.4 SMOSI/P1.5 SMISO/P1.6 P1.7 NC NC P0.7 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 P1.3/SSEL P1.2 VDD P1.1 P1.0 VSS P2.0 P2.1 P0.0/CLKIN P0.1/CLKOUT P0.2/INT0 P0.3/INT1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 NC P0.7 TIO1/P0.6 TIO0/P0.5 INT2/P0.4 INT1/P0.3 INT0/P0.2 CLKOUT\P0.1 CLKIN\P0.0 P2.1 P2.
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CY7C601xx CY7C602xx Pin Assignments Table 1. Pin Assignments 48 40 28 24 24 SSOP PDIP SSOP QSOP SOIC 7 24 PDIP 3 Name P4.0 6 2 P4.1 42 38 P4.2 43 39 P4.3 34 30 19 18 1 35 31 20 19 2 36 32 37 33 38 34 24 P3.4 39 35 25 P3.5 40 36 26 P3.6 41 37 27 P3.7 P3.0 Description GPIO Port 4—configured as a group (nibble) GPIO Port 3—configured as a group (byte) P3.1 P3.2 P3.3 15 11 11 11 18 P2.0 14 10 10 10 17 P2.1 13 9 P2.2 12 8 P2.
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CY7C601xx CY7C602xx Table 1. Pin Assignments (continued) 48 40 28 24 24 SSOP PDIP SSOP QSOP SOIC 24 PDIP Name Description 22 18 12 8 8 15 P0.1/CLKOUT GPIO Port 0 bit 1—Configured individually On CY7C601xx, optional clock out when external oscillator is disabled or external oscillator output drive when external oscillator is enabled. On CY7C602xx, oscillator output when configured as Clock Out. If this pin is used as a General Purpose output it will draw current.
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CY7C601xx CY7C602xx Register Summary enCoRe II LV Register Summary Addr Name 7 6 5 4 3 2 1 0 R/W Default 00 P0DATA P0.7 P0.6/TIO1 P0.5/TIO0 P0.4/INT2 P0.3/INT1 P0.2/INT0 P0.1/ CLKOUT P0.0/CLKIN bbbbbbbb 00000000 01 P1DATA P1.7 P1.4/SCLK P1.3/SSEL P1.2 P1.1 P1.0 bbbbbbbb 00000000 02 P2DATA P2.7–P2.2 P2.1–P2.0 bbbbbbbb 00000000 03 P3DATA P3.7–P3.2 P3.1–P3.
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CY7C601xx CY7C602xx enCoRe II LV Register Summary (continued) Addr Name 35 XOSCTR 36 LPOSCTR 3C SPIDATA 3D SPICR 7 6 5 4 3 32-kHz Low Power Reserved 32-kHz Bias Trim [1:0] Swap LSB First Comm Mode Reserved 2 XOSC XGM [2:0] 1 0 Reserved Mode 32-kHz Freq Trim [3:0] SPIData[7:0] DA INT_CLR0 GPIO Port 1 Sleep Timer INT1 GPIO Port 0 DB INT_CLR1 TCAP0 DC INT_CLR2 Reserved DE INT_MSK3 ENSWINT DF INT_MSK2 Reserved E1 INT_MSK1 TCAP0 Prog Interval 1-ms Timer Int Enable
PAGE 8
CY7C601xx CY7C602xx shift operations. The manner in which each flag is changed is dependent upon the instruction being executed (i.e., AND, OR, XOR). See Table 19. The Stack Pointer Register (CPU_SP) holds the address of the current top-of-stack in the data memory space. It is affected by the PUSH, POP, LCALL, CALL, RETI, and RET instructions, which manage the software stack. It can also be affected by the SWAP and ADD instructions.
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CY7C601xx CY7C602xx Index Register Table 5. CPU X Register (CPU_X) Bit # 7 6 5 4 Field 3 2 1 0 X [7:0] Read/Write – – – – – – – – Default 0 0 0 0 0 0 0 0 2 1 0 Bit [7:0]: X [7:0] 8-bit data value holds an index for any instruction that uses an indexed addressing mode. Stack Pointer Register Table 6.
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CY7C601xx CY7C602xx Examples Examples ADD A, 7 ;In this case, the immediate value of 7 is added with the Accumulator and the result is placed in the Accumulator. MOV X, 8 ;In this case, the immediate value of 8 is moved to the X register. AND F, 9 ADD A, [X+7] ;In this case, the value in the memory location at address X + 7 is added with the Accumulator, and the result is placed in the Accumulator.
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CY7C601xx CY7C602xx Table 16.Destination Direct Source Direct Destination Direct Source Immediate The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is the address of the result. The source for the instruction is Operand 2, which is an immediate value. Arithmetic instructions require two sources; the second source is the location specified by Operand 1. Instructions using this addressing mode are three bytes in length.
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CY7C601xx CY7C602xx Instruction Set Summary The instruction set is summarized in Table 19 numerically and serves as a quick reference. If more information is needed, the Instruction Set Summary tables are described in detail in the PSoC Designer Assembly Language User Guide (available on the www.cypress.com web site). Bytes Flags Cycles Instruction Format Opcode Hex Bytes Flags Cycles Instruction Format Opcode Hex Bytes Cycles Opcode Hex Table 19.
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CY7C601xx CY7C602xx Bytes Flags Cycles Instruction Format Opcode Hex Bytes Flags Cycles Instruction Format Opcode Hex Bytes Cycles Opcode Hex Table 19.
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CY7C601xx CY7C602xx Memory Organization Flash Program Memory Organization Figure 3.
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CY7C601xx CY7C602xx Data Memory Organization The CY7C601xx/CY7C602xx microcontrollers provide up to 256 bytes of data RAM Figure 4. Data Memory Organization after reset Address 8-bit PSP 0x00 Top of RAM Memory Stack begins here and grows upward 0xFF Flash This section describes the Flash block of the enCoRe II LV. Much of the user-visible Flash functionality, including programming and security, are implemented in the M8C Supervisory Read Only Memory (SROM).
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CY7C601xx CY7C602xx Two important variables that are used for all functions are KEY1 and KEY2. These variables are used to help discriminate between valid SSCs and inadvertent SSCs. KEY1 must always have a value of 3Ah, while KEY2 must have the same value as the stack pointer when the SROM function begins execution. This would be the Stack Pointer value when the SSC opcode is executed, plus three.
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CY7C601xx CY7C602xx The configuration of the WriteBlock function is straightforward. The BLOCKID of the Flash block, where the data is stored, must be determined and stored at SRAM address FAh. Table 25.EraseBlock Parameters The SRAM address of the first of the 64 bytes to be stored in Flash must be indicated using the POINTER variable in the parameter block (SRAM address FBh). Finally, the CLOCK and DELAY value must be set correctly.
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CY7C601xx CY7C602xx Table 27.ProtectBlock Parameters Name Address Description Table 29.
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CY7C601xx CY7C602xx Table 30.Checksum Parameters Name Address Table 31.Oscillator Trim Values vs. Voltage Settings Description KEY1 0,F8h 3Ah KEY2 0,F9h Stack Pointer value when SSC is executed BLOCKID 0,FAh Supervisory FLASH User Row Address Number of Flash blocks to calculate checksum on Function 0xC094 24-MHz IOSCTR @ 3.30V 0xC095 24-MHz IOSCTR @ 3.00V 0xC096 24-MHz IOSCTR @ 2.85V 0xC097 24-MHz IOSCTR @ 2.70V 0xC098 32-kHz LPOSCTR@3.30V Clocking 0xC099 32-kHz LPOSCTR@3.
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CY7C601xx CY7C602xx On the CY7C601xx, the external oscillator can be sourced by the crystal oscillator or when the crystal oscillator is disabled it is sourced directly from the CLKIN pin. The external crystal oscillator is fed through the EFTB block, which can optionally be bypassed. CPU Clock The CPU clock, CPUCLK, can be sourced from the external crystal oscillator, the Internal 24 MHz Oscillator, or the Internal 32 kHz Low-power Oscillator.
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CY7C601xx CY7C602xx Table 32.CPU Clock Config (CPUCLKCR) [0x30] [R/W] Bit # 7 6 5 Field 4 3 2 1 0 Reserved CPUCLK Select Read/Write – – – – – – – R/W Default 0 0 0 0 0 0 0 0 Bit [7:1]: Reserved Bit 0: CPU CLK Select 0 = Internal 24 MHz Oscillator. 1 = External crystal oscillator—External crystal oscillator on CLKIN and CLKOUT if the external crystal oscillator is enabled, CLKIN input if the external crystal oscillator is disabled.
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CY7C601xx CY7C602xx Table 34.Clock I/O Config (CLKIOCR) [0x32] [R/W] Bit # 7 6 5 Reserved Field 4 3 2 XOSC Select XOSC Enable EFTB Disabled 1 0 CLKOUT Select Read/Write – – – R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit [7:5]: Reserved Bit 4: XOSC Select This bit, when set, selects the external crystal oscillator clock as clock source of external clock. Care needs to be taken while selecting the crystal oscillator clock.
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CY7C601xx CY7C602xx Figure 6. Programmable Interval Timer Block Diagram Configuration Status and Control System Clock 12-bit reload value 12-bit down counter Clock Timer 12-bit reload control Interrupt Controller Timer Capture Clock (TCAPCLK) The Timer Capture clock (TCAPCLK) can be sourced from the external crystal oscillator, the Internal 24 MHz Oscillator or the Internal 32 kHz Low-power Oscillator. A programmable prescaler of 2, 4, 6, or 8 then divides the selected source. Figure 7.
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CY7C601xx CY7C602xx Table 35.Timer Clock Config (TMRCLKCR) [0x31] [R/W] Bit # 7 Field TCAPCLK Divider 6 5 4 TCAPCLK Select 3 2 1 ITMRCLK Divider 0 ITMRCLK Select Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 1 0 0 0 1 1 1 1 Bit [7:6]: TCAPCLK Divider [1:0] TCAPCLK Divider controls the TCAPCLK divisor.
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CY7C601xx CY7C602xx Internal Clock Trim Table 36.IOSC Trim (IOSCTR) [0x34] [R/W] Bit # 7 6 Field 5 4 3 foffset[2:0] 2 1 0 Gain[4:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 D D D D D The IOSC Calibrate register is used to calibrate the internal oscillator. The reset value is undefined but during boot the SROM writes a calibration value that is determined during manufacturing test. The “D” indicates that the default value is trimmed to 24 MHz @ 3.
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CY7C601xx CY7C602xx LPOSC Trim Table 38.LPOSC Trim (LPOSCTR) [0x36] [R/W] Bit # 7 6 Field 32 kHz Low Power Reserved 5 4 3 Read/Write R/W – R/W R/W R/W R/W R/W R/W Default 0 – D D D D D D 32 kHz Bias Trim [1:0] 2 1 0 32 kHz Freq Trim [3:0] This register is used to calibrate the 32 kHz Low-speed Oscillator. The reset value is undefined but during boot the SROM writes a calibration value that is determined during manufacturing test.
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CY7C601xx CY7C602xx Table 39.System Status and Control Register (CPU_SCR) [0xFF] [R/W] Bit # 7 6 5 4 3 2 1 0 Field GIES Reserved WDRS PORS Sleep Reserved Reserved Stop Read/Write R – R/C[3] R/C[3] R/W – – R/W Default 0 0 0 1 0 1 0 0 The bits of the CPU_SCR register are used to convey status and control of events for various functions of an enCoRe II LV device. Bit 7: GIES The Global Interrupt Enable Status bit is a read only status bit and its use is discouraged.
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CY7C601xx CY7C602xx Table 40.Reset Watchdog Timer (RESWDT) [0xE3] [W] Bit # 7 6 5 Field 4 3 2 1 0 Reset Watchdog Timer [7:0] Read/Write W W W W W W W W Default 0 0 0 0 0 0 0 0 Any write to this register will clear the Watchdog Timer, a write of 0x38 will also clear the Sleep Timer. Bit [7:0]: Reset Watchdog Timer [7:0] Sleep Mode sleep instruction is executed before the interrupt service routine (if enabled). The CPU can only be put to sleep by the firmware.
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CY7C601xx CY7C602xx Figure 8. Sleep Timing Firmware write to SCR SLEEP bit causes an immediate BRQ CPU captures BRQ on next CPUCLK edge CPU responds with a BRA On the falling edge of CPUCLK, PD is asserted. The 24/48 MHz system clock is halted; the Flash and bandgap are powered down CPUCLK IOW SLEEP BRQ BRA PD Wakeup Sequence Once asleep, the only event that can wake the system up is an interrupt. The global interrupt enable of the CPU flag register does not need to be set.
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CY7C601xx CY7C602xx Figure 9. Wakeup Timing S le e p T im e r o r G P IO in te rru p t o ccu rs In te rru p t is d o u b le sa m p le d b y 3 2 K clo ck a n d P D is n e g a te d to syste m C P U is re sta rte d a fte r 9 0 m s (n o m in a l) CLK32K IN T SLEEP PD BANDGAP ENABLE SAM PLE SAM PLE L V D /P O R CPUCLK/ 2 4M H z (N o t to S ca le ) BRQ BRA CPU Document 38-16016 Rev.
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CY7C601xx CY7C602xx Low-Voltage Detect Control Table 41.Low-voltage Control Register (LVDCR) [0x1E3] [R/W] Bit # 7 Field 6 5 Reserved 4 PORLEV[1:0] 3 2 Reserved 1 0 VM[2:0] Read/Write – – R/W R/W – R/W R/W R/W Default 0 0 0 0 0 0 0 0 This register controls the configuration of the Power-on Reset/Low-voltage Detection circuit. This register can only be accessed in the second bank of I/O space. This requires setting the XIO bit in the CPU flags register.
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CY7C601xx CY7C602xx ECO Trim Register Table 43.ECO (ECO_TR) [0x1EB] [R/W] Bit # Field 7 6 5 4 3 Sleep Duty Cycle [1:0] 2 1 0 Reserved Read/Write R/W R/W – – – – – – Default 0 0 0 0 0 0 0 0 This register controls the ratios (in numbers of 32 kHz clock periods) of “on” time versus “off” time for LVD and POR detection circuit.
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CY7C601xx CY7C602xx P1 Data Table 45.P1 Data Register (P1DATA) [0x01] [R/W] Bit # 7 6 5 4 3 2 1 0 Field P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P1.3/SSEL P1.2 P1.1 P1.0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 This register contains the data for Port 1. Writing to this register sets the bit values to be output on output enabled pins. Reading from this register returns the current state of the Port 1 pins. Bit 7: P1.7 Data Bit [6:3]: P1.6–P1.
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CY7C601xx CY7C602xx GPIO Port Configuration When clear, the output can sink up to 8 mA. All the GPIO configuration registers have common configuration controls. The following are the bit definitions of the GPIO configuration registers. By default all GPIOs are configured as inputs. In order to prevent the inputs from floating the pull up resistors are enabled. Firmware will need to configure each of the GPIOs prior to use. On the CY7C601xx, only the P3.7, P2.7, P0.1, and P0.
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CY7C601xx CY7C602xx P0.0/CLKIN Configuration Table 49.P0.0/CLKIN Configuration (P00CR) [0x05] [R/W] Bit # 7 6 5 4 3 2 1 0 Field Reserved Int Enable Int Act Low TTL Thresh High Sink Open Drain Pull-up Enable Output Enable Read/Write – R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 This pin is shared between the P0.0 GPIO use and the CLKIN pin for the external crystal oscillator. When the external oscillator is enabled the settings of this register are ignored.
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CY7C601xx CY7C602xx P0.2/INT0–P0.4/INT2 Configuration Table 51.P0.2/INT0–P0.4/INT2 Configuration (P02CR–P04CR) [0x07–0x09] [R/W] Bit # 7 Field 6 Reserved 5 4 3 2 1 0 Int Act Low TTL Thresh Reserved Open Drain Pull-up Enable Output Enable Read/Write – – R/W R/W – R/W R/W R/W Default 0 0 0 0 0 0 0 0 These registers control the operation of pins P0.2–P0.4 respectively. These pins are shared between the P0.2–P0.4 GPIOs and the INT0–INT2.
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CY7C601xx CY7C602xx P1.0 Configuration Table 54.P1.0 Configuration (P10CR) [0x0D] [R/W] Bit # 7 6 5 Field Reserved Int Enable Int Act Low 4 3 Read/Write R/W R/W R/W – – Default 0 0 0 0 0 2 1 0 P1.0 and P1.1 Pull Up Enable Output Enable – – R/W 0 0 0 Reserved This register controls the operation of the P1.0 pin. Bit1: P1.0 and P1.1 Pull Up Enable 0 = Disable the P1.0 and P1.1 pull up resistors 1 = Enable the internal pull up resistors for both the P1.0 and P1.1.
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CY7C601xx CY7C602xx P1.3 Configuration (SSEL) Table 57.P1.3 Configuration (P13CR) [0x10] [R/W] Bit # 7 6 5 4 3 2 1 0 Field Reserved Int Enable Int Act Low Reserved High Sink Open Drain Pull Up Enable Output Enable Read/Write – R/W R/W – R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 This register controls the operation of the P1.3 pin. The P1.3 GPIO’s threshold is always set to TTL.
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CY7C601xx CY7C602xx P2 Configuration Table 60.P2 Configuration (P2CR) [0x15] [R/W] Bit # 7 6 5 4 3 2 1 0 Field Reserved Int Enable Int Act Low TTL Thresh High Sink Open Drain Pull Up Enable Output Enable Read/Write – R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 In CY7C602xx this register controls the operation of pins P2.0–P2.1. In the CY7C601xx, this register controls the operation of pins P2.0–P2.7. The 50-mA sink drive capability is only available on pin P2.
PAGE 40
CY7C601xx CY7C602xx Serial Peripheral Interface (SPI) The SPI Master/Slave Interface core logic runs on the SPI clock domain. The SPI clock is a divider off of the CPUCLK when in Master Mode. SPI is a four-pin serial interface comprised of a clock, an enable, and two data pins. Figure 11.
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CY7C601xx CY7C602xx SPI Data Register Table 63.SPI Data Register (SPIDATA) [0x3C] [R/W] Bit # 7 6 5 4 Field 3 2 1 0 SPIData[7:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 When read, this register returns the contents of the receive buffer. When written, it loads the transmit holding register.
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CY7C601xx CY7C602xx Table 65.SPI Mode Timing vs.
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CY7C601xx CY7C602xx clock. The 16-bit free-running counter is used as the time-base for timer captures and can also be used as a general timebase by software. Table 66.SPI SCLK Frequency SCLK CPUCLK Select Divisor SCLK Frequency when CPUCLK = 12 MHz 00 6 2 MHz Registers 01 12 1 MHz Free-running Counter The 16 bit free-running counter is clocked by the Timer Capture Clock (TCAPCLK). It can be read in software for use as a general-purpose time base.
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CY7C601xx CY7C602xx Table 68.Free-running Timer High-order Byte (FRTMRH) [0x21] [R/W] Bit # 7 6 5 Field 4 3 2 1 0 Free Running Timer [15:8] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit [7:0]: Free-running Timer [15:8] When reading the Free-running Timer, the low-order byte should be read first and the high-order second. When writing, the loworder byte should be written first then the high-order byte.
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CY7C601xx CY7C602xx Table 70.
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CY7C601xx CY7C602xx Table 74.Timer Capture 1 Falling (TCAP1F) [0x25] [R/W] Bit # 7 6 5 Field 4 3 2 1 0 Capture 1 Falling [7:0] Read/Write R R R R R R R R Default 0 0 0 0 0 0 0 0 Bit [7:0]: Capture 1 Falling [7:0] This register holds the value of the Free-running Timer when the last falling edge occurred on the TCAP1 input. The bits that are stored here are selected by the Prescale [2:0] bits in the Timer Configuration register.
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CY7C601xx CY7C602xx Table 78.Programmable Interval Reload Low (PIRL) [0x28] [R/W] Bit # 7 6 5 Field 4 3 2 1 0 Prog Interval [7:0] Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit [7:0]: Prog Interval [7:0] This register holds the lower 8 bits of the timer. While writing into the 12-bit reload register, write lower byte first then the higher nibble. Table 79.
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CY7C601xx CY7C602xx Figure 15. 16-bit Free Running Counter Loading Timing Diagram clk_sys write valid addr write data FRT reload ready Clk Timer 12b Prog Timer 12b reload interrupt 12-bit programmable timer load timing Capture timer clk 16b free running counter load 16b free running counter 00A0 00A1 00A2 00A3 00A4 00A5 00A6 00A7 00A8 00A9 00AB 00AC 00AD 00AE 00AF 00B0 00B1 00B2 ACBE ACBF ACC0 16-bit free running counter loading timing Figure 16.
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CY7C601xx CY7C602xx Interrupt Controller Table 80.Interrupt Priorities, Address, Name (continued) The interrupt controller and its associated registers allow the user’s code to respond to an interrupt from almost every functional block in the enCoRe II LV devices. The registers associated with the interrupt controller allow to be disabled either globally or individually.
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CY7C601xx CY7C602xx 5. The ISR executes. Note that interrupts are disabled since GIE = 0. In the ISR, interrupts can be re-enabled if desired by setting GIE = 1 (care must be taken to avoid stack overflow). 6. The ISR ends with a RETI instruction which restores the Program Counter and Flag registers (CPU_PC and CPU_F). The restored Flag register re-enables interrupts, since GIE = 1 again. 7. Execution resumes at the next instruction, after the one that occurred before the interrupt.
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CY7C601xx CY7C602xx Table 82. Interrupt Clear 1 (INT_CLR1) [0xDB] [R/W] Bit # 7 6 5 Field TCAP0 Prog Interval Timer 1-ms Programmable Interrupt 4 3 Read/Write R/W R/W R/W – – Default 0 0 0 0 0 2 1 0 – – – 0 0 0 Reserved When reading this register, 0 = There’s no posted interrupt for the corresponding hardware 1 = Posted interrupt for the corresponding hardware present Writing a ‘0’ to the bits will clear the posted interrupts for the corresponding hardware.
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CY7C601xx CY7C602xx Table 85.
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CY7C601xx CY7C602xx Table 87.
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CY7C601xx CY7C602xx Absolute Maximum Ratings Maximum Total Sink Output Current into Port 0 and 1 and Pins............................................................. 70 mA Storage Temperature ................................. –65°C to +150°C Maximum Total Source Output Current into GPIO Pins30 mA Ambient Temperature with Power Applied ..... –0°C to +70°C Supply Voltage on VCC Relative to VSS ......... –0.5V to +7.0V Maximum On-chip Power Dissipation on any GPIO Pin....................................
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CY7C601xx CY7C602xx AC Characteristics (continued) Parameter Description Conditions Min. Typical Max. Unit 2 MHz 2.
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CY7C601xx CY7C602xx Figure 20. SPI Master Timing, CPHA = 1 SS (SS is under firmware control in SPI Master mode) TSCKL SCK (CPOL=0) TSCKH SCK (CPOL=1) TMDO MSB MOSI MSB MISO LSB LSB TMSU TMHD Figure 21. SPI Slave Timing, CPHA = 1 SS TSSS TSSH TSCKL SCK (CPOL=0) TSCKH SCK (CPOL=1) MOSI MSB TSDO MISO Document 38-16016 Rev.
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CY7C601xx CY7C602xx Figure 22. SPI Master Timing, CPHA = 0 SS (SS is under firmware control in SPI Master mode) TSCKL SCK (CPOL=0) TSCKH SCK (CPOL=1) TMDO TMDO1 MSB MOSI LSB MSB MISO LSB TMSU TMHD Figure 23. SPI Slave Timing, CPHA = 0 SS TSSH TSSS TSCKL SCK (CPOL=0) TSCKH SCK (CPOL=1) MSB MOSI LSB TSSU TSHD TSDO TSDO1 MISO Document 38-16016 Rev.
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CY7C601xx CY7C602xx 1 Ordering Information Ordering Code FLASH Size RAM Size Package Type CY7C60123-PVXC 8K 256 48-SSOP CY7C60123-PXC 8K 256 40-PDIP CY7C60113-PVXC 8K 256 28-SSOP CY7C60223-PXC 8K 256 24-PDIP CY7C60223-SXC 8K 256 24-SOIC CY7C60223-QXC 8K 256 24-QSOP Package Diagrams Figure 24. 24-Lead (300-Mil) SOIC S13 NOTE : 1. JEDEC STD REF MO-119 PIN 1 ID 2.
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CY7C601xx CY7C602xx Package Diagrams (continued) Figure 25. 24-Lead (300-Mil) PDIP P13 51-85013-*B Figure 26. 24-lead QSOP O241 0.033 REF. 12 0.228 1 PIN 1 ID 0.150 0.157 DIMENSIONS IN INCHES MIN. MAX. 0.244 13 24 0.337 0.344 SEATING PLANE 0.007 0.010 0.053 0.069 0.004 0.004 0.010 Document 38-16016 Rev. *C 0.008 0.012 0.025 BSC. 0.016 0.
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CY7C601xx CY7C602xx Package Diagrams (continued) Figure 27. 28-Lead (5.3 mm) Shrunk Small Outline Package O28 51-85079-*C Figure 28. 40-Lead (600-Mil) Molded DIP P17 51-85019-*A Document 38-16016 Rev.
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CY7C601xx CY7C602xx Package Diagrams (continued) Figure 29. 48-Lead Shrunk Small Outline Package O48 51-85061-*C PSoC is a registered trademark and enCoRe is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document 38-16016 Rev. *C Page 61 of 62 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice.
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CY7C601xx CY7C602xx Document History Page Document Title: CY7C601/2xx enCoRe™ II Low Voltage Microcontroller Document Number: 38-16016 Rev. ECN No. Issue Date Orig.