User manual

CY8C29466, CY8C29566
CY8C29666, CY8C29866
Document Number: 38-12013 Rev. *M Page 42 of 47
13.1 Thermal Impedances 13.2 Capacitance on Crystal Pins
13.3 Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 13-1. Thermal Impedances per Package
Package Typical θ
JA
*
28 PDIP 69
o
C/W
28 SSOP 94
o
C/W
28 SOIC 67
o
C/W
44 TQFP 60
o
C/W
48 SSOP 69
o
C/W
48 QFN** 28
o
C/W
100 TQFP 50
o
C/W
* T
J
= T
A
+ POWER x θ
JA
** To achieve the thermal impedance specified for the QFN package, the center
thermal pad should be soldered to the PCB ground plane.
Table 13-2. Typical Package Capacitance on Crystal Pins
Package Package Capacitance
28 PDIP 3.5 pF
28 SSOP 2.8 pF
28 SOIC 2.7 pF
44 TQFP 2.6 pF
48 SSOP 3.3 pF
48 QFN 1.8 pF
100 TQFP 3.1 pF
Table 13-3. Solder Reflow Peak Temperature
Package
Minimum Peak Tempera-
ture*
Maximum Peak Temperature
28 PDIP 220
o
C 260
o
C
28 SSOP 240
o
C 260
o
C
28 SOIC 220
o
C 260
o
C
44 TQFP 220
o
C 260
o
C
48 SSOP 220
o
C 260
o
C
48 QFN 220
o
C 260
o
C
100 TQFP 220
o
C 260
o
C
*Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5
o
C
with Sn-Pb or 245 ± 5
o
C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications.
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