User manual

CY8C29466, CY8C29566
CY8C29666, CY8C29866
Document Number: 38-12013 Rev. *M Page 32 of 47
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.
Figure 12-10. Typical AGND Noise with P2[4] Bypass
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Table 12-20. 3.3V AC Operational Amplifier Specifications
Symbol Description Min Typ Max Units
T
ROA
Rising Settling Time to 0.1% of a 1V Step (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
3.92
0.72
μs
μs
T
SOA
Falling Settling Time to 0.1% of a 1V Step (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
5.41
0.72
μs
μs
SR
ROA
Rising Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High 0.31
2.7
V/
μs
V/
μs
SR
FOA
Falling Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High 0.24
1.8
V/
μs
V/
μs
BW
OA
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
0.67
2.8
MHz
MHz
E
NOA
Noise at 1 kHz (Power = Medium, Opamp Bias = High) 100 nV/rt-Hz
100
1000
10000
0.001 0.01 0.1 1 10 100Freq ( kHz)
dBV/rtHz
0
0.01
0.1
1.0
10
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