User manual

CY8C27143, CY8C27243
CY8C27443, CY8C27543, CY8C27643
Document Number: 38-12012 Rev. *O Page 33 of 53
Figure 12. PLL Lock Timing Diagram
Figure 13. PLL Lock for Low Gain Setting Timing Diagram
Figure 14. External Crystal Oscillator Startup Timing Diagram
Figure 15. 24 MHz Period Jitter (IMO) Timing Diagram
Figure 16. 32 kHz Period Jitter (ECO) Timing Diagram
T
POWERUP
Time from end of POR to CPU
executing code
16 100 ms Power up from 0V. See the
System Resets section of the
PSoC Technical Reference
Manual.
Fout
48M
48 MHz Output Frequency 46.8 48.0 49.2
[13,15]
MHz Trimmed. Utilizing factory trim
values.
Jitter
24M1
24 MHz Period Jitter (IMO) 600 ps
F
MAX
Maximum frequency of signal on row
input or row output.
12.3 MHz
SR
POWER_UP
Power Supply Slew Rate 250 V/ms Vdd slew rate during power up.
Table 31. AC Chip-Level Specifications (continued)
Symbol Description Min Typ Max Unit Notes
24 MHz
F
PLL
PLL
Enable
T
PLLSLEW
PLL
Gain
0
24 MHz
F
PLL
PLL
Enable
T
PLLSLEWLOW
PLL
Gain
1
32 kHz
F
32K2
32K
Select
T
OS
Jitter24M1
F
24M
Jitter32k
F
32K2
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