User manual
CY8C27143, CY8C27243
CY8C27443, CY8C27543, CY8C27643
Document Number: 38-12012 Rev. *O Page 13 of 53
Table 8. 48-Pin Part Pinout (QFN)*
Pin
No.
Type
Pin
Name
Description
Figure 8. CY8C27643 48-Pin PSoC Device
Digital Analog
1 I/O I P2[3] Direct switched capacitor block input.
2 I/O I P2[1] Direct switched capacitor block input.
3 I/O P4[7]
4 I/O P4[5]
5 I/O P4[3]
6 I/O P4[1]
7 Power SMP Switch Mode Pump (SMP) connection to
external components required.
8 I/O P3[7]
9 I/O P3[5]
10 I/O P3[3]
11 I/O P3[1]
12 I/O P5[3]
13 I/O P5[1]
14 I/O P1[7] I2C Serial Clock (SCL).
15 I/O P1[5] I2C Serial Data (SDA).
16 I/O P1[3]
17 I/O P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK**.
18 Power Vss Ground connection.
19 I/O P1[0] Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA**.
20 I/O P1[2]
21 I/O P1[4] Optional External Clock Input (EXTCLK).
22 I/O P1[6]
23 I/O P5[0]
24 I/O P5[2]
25 I/O P3[0]
26 I/O P3[2]
27 I/O P3[4]
28 I/O P3[6]
29 Input XRES Active high external reset with internal pull
down.
30 I/O P4[0]
31 I/O P4[2]
32 I/O P4[4]
33 I/O P4[6]
34 I/O I P2[0] Direct switched capacitor block input.
35 I/O I P2[2] Direct switched capacitor block input.
36 I/O P2[4] External Analog Ground (AGND).
37 I/O P2[6] External Voltage Reference (VRef).
38 I/O I P0[0] Analog column mux input.
39 I/O I/O P0[2] Analog column mux input and column output.
40 I/O I/O P0[4] Analog column mux input and column output.
41 I/O I P0[6] Analog column mux input.
42 Power Vdd Supply voltage.
43 I/O I P0[7] Analog column mux input.
44 I/O I/O P0[5] Analog column mux input and column output.
45 I/O I/O P0[3] Analog column mux input and column output.
46 I/O I P0[1] Analog column mux input.
47 I/O P2[7]
48 I/O P2[5]
LEGEND: A = Analog, I = Input, and O = Output.
* The QFN package has a center pad that must be connected to ground (Vss).
** These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Mixed-Signal Array Technical Reference Manual for details.
QFN
(Top View)
P2[5]
P2[7]
P 0[1 ], A , I
P 0[3 ], A , IO
P 0[5 ], A , IO
P 0[7 ], A , I
Vdd
P 0[6 ], A , I
P 0[4 ], A , IO
P 0[2 ], A , IO
P 0[0 ], A , I
P2[6], External VRef
10
11
12
A, I, P2[3]
A, I, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
35
34
33
32
31
30
29
28
27
26
25
36
48
47
46
45
44
43
42
41
40
39
38
37
P2[2], A, I
P2[0], A, I
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
P3[0]
P2[4], External AGND
1
2
3
4
5
6
7
8
9
13
14
15
16
17
18
19
20
21
22
23
24
P5[1]
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
I2C SDA, XTALout, P1[0]
P1[2]
EXTCLK, P1[4]
P1[6]
P5[0]
P5[2]
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